Emmanuel Dubois

High Gain and Fast Detection of Warfare Agents Using Back-Gated Silicon-Nanowired MOSFETs

The top-down fabrication of doped p-type silicon-nanowired (NW) arrays and their application as gas detectors is presented. After surface functionalization with 3-(4-ethynylbenzyl)-1, 5, 7-trimethyl-3-azabicyclo [3.3.1] nonane-7-methanol molecules, the wires were subjected to an organophosphorous simulant, and both static and dynamic measurements were performed. A current gain of 4 × 106 is obtained upon the detection of the subpart-per-million concentration of a nerve-agent simulant. This represents a four-decade improvement over previous demonstration based on nanoribbons, proving better sensing capabilities of NWs. Technology-computer-aided-design simulations before and after gas detection have been performed to gain insight into the physical mechanisms involved in the gas detection and to investigate the impact of the surface-to-volume ratio on sensor sensitivity.

Integration of PtSi in p-Type MOSFETs Using a Sacrificial Low-Temperature Germanidation Process

In this letter, an original selective etching method of Pt with respect to PtSi using a sacrificial low-temperature germanidation process is used for the integration of valence band edge contacts in p-type MOSFET devices. After silicidation annealing, the excess of Pt due to incomplete reaction with silicon or standing on insulating layers can be transformed into the PtGe2 phase. The solubility of this phase in a sulfuric peroxide mixture (SPM) without altering PtSi is demonstrated. The suitability and scalability of the proposed integration scheme is shown through the successful integration and characterization of PtSi source/drain contacts in p-type MOSFETs.

CMOS Integration Using Low Thermal Budget Dopant-Segregated Metallic S/D Junctions on Thin-Body SOI

1-Introduction: Thin-body MOSFET architectures associated to upcoming technology nodes are expected to deliver a higher current drive at shallower junction depth and reduced silicide thickness. As a result, extremely severe constraints are placed on the junction and contact technologies. One alternative is to use silicided metallic contacts that present a very low effective Schottky barrier height (SBH) to electrons and holes for n-type and p-type MOSFETs, respectively. Considering that the equivalent SBH should not exceed 0.1 eV in order to position SBMOSFETs advantageously with respect to conventional technology [1], low temperature dopant segregation (DS) at the Schottky interface has emerged as a sound technological solution. The most advantageous methodology is to combine a band-edge silicide to its appropriate dopant type. In that way, p-type MOSFETs with boron segregated PtSi contacts have been demonstrated [2]. Conversely, a conduction band-edge silicide coupled to segregated donor impurities is desirable for n-MOSFETs [3]. However, this last approach faces two major obstacles: i) the integration of a second silicide material and ii) difficulties to process high quality rare-earth silicides layers [4-5]. Although, a material like PtSi that presents a large SBH to electrons is theoretically not attractive for n-MOS devices, it proved to produce a near 0.1eV when combined to As segregation [6]. Following this integration route, 0.35μm gate length MOSFETs of both polarities were also integrated [6]. Although dopant segregated contacts in complementary MOS were previously published based on midgap silicides [7-8], implantation before silicidation (IBS) and high temperature activation suppressed the advantage of low temperature processing. In this paper, As and B segregated PtSi contacts are integrated in the socalled implant-through-silicide (ITS) flavour down to 70 nm of gate length. Functional elementary inverters are demonstrated in both DC and transient modes. 2SB height modulation: experiments and characterization: Dedicated test structures consisting in two silicided backto-back junctions separated by a micrometer gap have been fabricated on n-type (100) Si wafers. Starting from a 20 nm thick Pt layer, the subsequent silicidation reaction was activated by rapid thermal annealing (RTA) at 350°C for 3 min before As implantation at 20 keV with a dose of 10 cm. A RTA post-anneal activates the mechanism of As segregation. SIMS profiles show how arsenic accumulates at the PtSi/Si interface when the post annealing temperature increases from 400 to 700°C. It is observed a sharp As peak concentration around 4 10 cm at 500°C and above. The accurate extraction of SB heights is based on a procedure which gives a precise extraction of extremely low SBH by coupling experiments data from diode structures with a transport model including thermionic, tunnel emission and barrier lowering due to image charge induction [9]. SBH below 80 meV for nand p-type are obtained with activation at 600°C. 3n-MOS performance and CMOS integration: The Ids-Vgs characteristic shows how arsenic segregated PtSi source/drain improve operation when a post silicidation threshold temperature of 600°C is reached. Such thermal activation provides a SBH to electrons of 70meV which do not limit carrier injection as illustrated by the Ion vs Lg trend line. It is also demonstrated that the As-DS junctions do not degrade the subthreshold swing and DIBL. A comparison to the state-of-the-art of metallic Schottky S/D n-MOSFETs places the Assegregated ITS scheme with PtSi in a competitive position. Only particular channel architectures (i.e. FinFET) outperform the presented results. Arsenic (nMOS) and boron (p-MOS) segregated PtSi junctions have been integrated in a single low temperature (600°C) process and CMOS inverters have been successfully fabricated. Based on Ids-Vgs and Ids-Vds characteristics of 70 nm gate long nand p-MOSFETs, current drives for nand p-type devices of 596/378 μA/μm at VDD=1.1V (with |Vg|=2V to account for the 2.4 nm gate oxide thickness) have been obtained. Based on the above devices, inverters with nearly ideal DC voltage transfer characteristics and large voltage gains have been obtained down to 0.5V of supply voltage with excellent noise margins (~VDD/2). The dynamic response at 10 MHz of a 70nm CMOS inverter shows excellent regenerative properties. 4Conclusion: This approach provides a low temperature S/D module suitable for a viable and low-cost manufacturing approach for future CMOS technology nodes. In summary, one major improvement compared to the conventional ohmic contact is to reach similar performance with a huge process simplification. Conventional transistor architectures in the sub-22nm regime require junctions with ultrasharp doping concentration gradient. This imposes the development of very sophisticated annealing techniques and also leads to tight thermal constraints on constituent materials. Conversely, the proposed integration scheme can be qualified as a cold process, without high temperature dopants activation, that leverages many constraints associated to the integration of innovative gate stacks comprising high-K dielectric and metal gate.

Iridium Silicide: a Promising Electrode for Metallic Source/Drain in Decananometer MOSFETs

A detailed study of the formation of iridium like silicide obtained on ultra high vacuum annealing and on rapid thermal annealing is proposed using x-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and electrical characterizations. Using XPS analysis, the stochiometry of silicidation (IrSi, IrSi1.6) is identified. A very uniform IrSi layer obtained at low temperature gave a lower Schottky barrier height than a PtSi silicide. Lastly, the IrSix phase, obtained at 900{degree sign}C, proposed a very poor film quality.