Guilhem Larrieu

Gold-free growth of GaAs nanowires on silicon: arrays and polytypism

We report growth by molecular beam epitaxy and structural characterization of gallium-nucleated GaAs nanowires on silicon. The influences of growth temperature and V/III ratio are investigated and compared in the case of oxide-covered and oxide-free substrates. We demonstrate a precise positioning process for Ga-nucleated GaAs nanowires using a hole array in a dielectric layer thermally grown on silicon. Crystal quality is analyzed by high resolution transmission electron microscopy. Crystal structure evolves from pure zinc blende to pure wurtzite along a single nanowire, with a transition region.

A combination of capillary and dielectrophoresis-driven assembly methods for wafer scale integration of carbon-nanotube-based nanocarpets

The wafer scale integration of carbon nanotubes (CNT) remains a challenge for electronic and electromechanical applications. We propose a novel CNT integration process relying on the combination of controlled capillary assembly and buried electrode dielectrophoresis (DEP). This process enables us to monitor the precise spatial localization of a high density of CNTs and their alignment in a pre-defined direction. Large arrays of independent and low resistivity (4.4 × 10(-5) Ω m) interconnections were achieved using this hybrid assembly with double-walled carbon nanotubes (DWNT). Finally, arrays of suspended individual CNT carpets are realized and we demonstrate their potential use as functional devices by monitoring their resonance frequencies (ranging between 1.7 and 10.5 MHz) using a Fabry-Perot interferometer.

Modelling and engineering of stress based controlled oxidation effects for silicon nanostructure patterning.

Silicon nanostructure patterning with tight geometry control is an important challenge at the bottom level. In that context, stress based controlled oxidation appears to be an efficient tool for precise nanofabrication. Here, we investigate the stress-retarded oxidation phenomenon in various silicon nanostructures (nanobeams, nanorings and nanowires) at both the experimental and the theoretical levels. Different silicon nanostructures have been fabricated by a top-down approach. Complex dependence of the stress build-up on the nano-objects dimension, shape and size has been demonstrated experimentally and physically explained by modelling. For the oxidation of a two-dimensional nanostructure (nanobeam), relative independence to size effects has been observed. On the other hand, radial stress increase with geometry downscaling of a one-dimensional nanostructure (nanowire) has been carefully emphasized. The study of shape engineering by retarded oxidation effects for vertical silicon nanowires is finally discussed.

Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array

A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations both in processing (layer engineering at nanoscale), in electrical properties (high electrostatic control, low defect level, multi-Vt platform) in the fabrication of CMOS inverters and in the perspective of ultimate scaling.

Thin-dielectric-layer engineering for 3D nanostructure integration using an innovative planarization approach

Three-dimensional (3D) nanostructures are emerging as promising building blocks for a large spectrum of applications. One critical issue in integration regards mastering the thin, flat, and chemically stable insulating layer that must be implemented on the nanostructure network in order to build striking nano-architectures. In this letter, we report an innovative method for nanoscale planarization on 3D nanostructures by using hydrogen silesquioxane as a spin-on-glass (SOG) dielectric material. To decouple the thickness of the final layer from the height of the nanostructure, we propose to embed the nanowire network in the insulator layer by exploiting the planarizing properties of the SOG approach. To achieve the desired dielectric thickness, the structure is chemically etched back with a highly diluted solution to control the etch rate precisely. The roughness of the top surface was less than 2 nm. There were no surface defects and the planarity was excellent, even in the vicinity of the nanowires. This newly developed process was used to realize a multilevel stack architecture with sub-deca-nanometer-range layer thickness.

Evolutionary multi-objective optimization for multi-resonant photonic nanostructures

The tailoring of optical properties of photonic nanostructures is usually based on a reference design. The target optical behavior is obtained by variations of an initial geometry. This approach however can be of limited versatility, in particular if complex optical properties are desired. In order to design double-resonant photonic nano-particles, we attack the problem in the inverse way: We mathematically define an optical response and optimize multiple of such objective functions concurrently, using an evolutionary multi-objective optimization algorithm coupled to full-field electro-dynamical simulations. We demonstrate that this approach is extremely versatile, that it allows the consideration of technological limitations and that it yields a correct prediction of the optical response of nano-structures fabricated by state-of-the-art electron beam lithography. We demonstrate the technique on multi-resonant photonic nanoparticles made from silicon, which belong to the emerging class of high refractive index dielectric nanostructures with applications such as field-enhanced spectroscopies.

A self-aligned functionalization approach to order neuronal networks at the single cell level.

Despite significant progress, our knowledge of the functioning of the central nervous system still remains scarce to date. A better understanding of its behavior, in either normal or diseased conditions, goes through an increased knowledge of basic mechanisms involved in neuronal function, including at the single-cell level. This has motivated significant efforts for the development of miniaturized sensing devices to monitor neuronal activity with high spatial and signal resolution. One of the main challenges remaining to be addressed in this domain is, however, the ability to create in vitro spatially ordered neuronal networks at low density with a precise control of the cell location to ensure proper monitoring of the activity of a defined set of neurons. Here, we present a novel self-aligned chemical functionalization method, based on a repellant surface with patterned attractive areas, which permits the elaboration of low-density neuronal network down to individual cells with a high control of the soma location and axonal growth. This approach is compatible with complementary metal-oxide-semiconductor line technology at a wafer scale and allows performing the cell culture on packaged chip outside microelectronics facilities. Rat cortical neurons were cultured on such patterned surfaces for over one month and displayed a very high degree of organization in large networks. Indeed, more than 90% of the network nodes were settled by a soma and 100% of the connecting lines were occupied by a neurite, with a very good selectivity (low parasitic cell connections). After optimization, networks composed of 75% of unicellular nodes were obtained, together with a control at the micron scale of the location of the somas. Finally, we demonstrated that the dendritic neuronal growth was guided by the surface functionalization, even when micrometer scale topologies were encountered and we succeeded to control the extension growth along one-dimensional-aligned nanostructures with sub-micrometrical scale precision. This novel approach now opens the way for precise monitoring of neuronal network activity at the single-cell level.

Multi-resonant silicon nanoantennas by evolutionary multi-objective optimization

Photonic nanostructures have attracted a tremendous amount of attention in the recent past. Via their size, shape and material it is possible to engineer their optical response to user-defined needs. Tailoring of the optical response is usually based on a reference geometry for which subsequent variations to the initial design are applied. Such approach, however, might fail if optimum nanostructures for complex optical responses are searched. As example we can mention the case of complex structures with several simultaneous optical resonances. We propose an approach to tackle the problem in the inverse way: In a first step we define the desired optical response as function of the nanostructure geometry. This response is numerically evaluated using the Green Dyadic Method for fully retarded electro-dynamical simulations. Eventually, we optimize multiple of such objective functions concurrently, using an evolutionary multi-objective optimization algorithm, which is coupled to the electro-dynamical simulations code. A great advantage of this optimization technique is, that it allows the implicit and automatic consideration of technological limitations like the electron beam lithography resolution. Explicitly, we optimize silicon nanostructures such that they provide two user-defined resonance wavelengths, which can be individually addressed by crossed incident polarizations.

1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors

Low-frequency noise characteristics have been investigated in arrays of 14 nm gate-all-around vertical silicon junction-less nanowire transistors. Extensive measurements have been performed to study the evolution of the 1/f noise as a function of bias for nanowire arrays with different nanowire diameters and several numbers of nanowires in parallel. Measured drain current noise can be explained well by correlated mobility fluctuation noise theory. Although the conduction is mainly limited by the bulk, i.e., the core of the nanowire, additional trapping/release of charge carriers is observed due to an accumulation channel formed at higher gate bias. Additionally, for the first time in junction-less transistors, evidence of significant noise contribution from access regions at higher bias is observed that provides insight into 1/f noise origin.

Enhanced nonlinear optical properties from individual silicon nanowires

We study second harmonic generation (SHG) from individual silicon nanowires. We show that second harmonic intensity is strongly dependent on the Mie resonances supported by the nanowire. The second harmonic polarization also has a size-dependent behavior, which is linked to different surface and bulk-like nonlinear susceptibility contributions. Silicon nanowires provide an interesting tool for nonlinear photonics applications.