Emrah Onat

Automated fixed-point precision optimization

An algorithm which minimizes the hardware resources of fixed-point operations for a given accuracy is presented. For range analysis, forward propagation is used in order to determine the ranges of the intermediate signals. For the precision analysis, a search algorithm is used. Analytical quantization error models are used with the precision search algorithm. The main novelty of this work is the use of the weighted search algorithm which can minimize the hardware resources for a specific FPGA. By using weights, the search algorithm is modified to produce an optimum result for the target FPGA for a specific hardware resource such as multipliers or blok rams.

Traffic sign classification using hough transform and SVM

In this paper, classification of traffic signs in Turkey with the help of their some features such as color and shape is explained. In the algorithm that is generated in MATLAB, firstly trafic signs are distinguished from the other objects of the image and then filtered by their colors. After filtering, edge detection is processed and then Hough Transform and SVM are used for shape classification.

Implementation of Doppler noise jamming techniques using DRFM

In this paper, hardware implementation of Doppler noise and narrow band Doppler noise techniques those are jamming of Doppler frequency based on FPGA is explained. Pulse Doppler radar signal generator and receiver parts and algorithms of techniques are implemented on the Xilinx Virtex-4 FPGA. Besides, effective jamming to signal ratios of Doppler noise and narrow band Doppler noise techniques are compared.

Implementation of digital pulse doppler radar signal generator and receiver

In this paper, hardware implementation of digital pulse Doppler radar signals generator and receiver based on FPGA is explained. Different performances have been noticed while using CORDIC and Hilbert transform cores for the phase shifter blocks in the implementation of generator and receiver parts. Algorithms are implemented on the Xilinx Virtex-4 FPGA. Required hardware area, resolution and amplitude of Doppler frequency at the output of the receiver are compared for different implementation with altering the phase shifter block.

FPGA implementation of real time video signal processing using Sobel, Robert, Prewitt and Laplacian filters

In this paper, hardware implementation of edge detection at real time video signals using Sobel, Robert, Prewitt and Laplacian filters based on FPGA is explained. Besides, filters are compared in many ways. Edge detection is an elemantary and fundamental tool for image segmentation and feature extraction. Very high speed hardware like FPGAs are used to implement the image and video processing algorithms for improving the performance of processing systems. Algorithms are implemented on the Xilinx Zynq 7000. The video input signals come from a laptops HDMI interface to FPGA in order to filter and the detected edges are displayed on a HDMI display screen.

Amplitude and phase difference tolerance analysis of cross-eye jamming technique

In this paper, amplitude and phase difference tolerance analysis for cross-eye angle deception technique that used against monopulse radars is prestented. Amplitude and phase difference tolerance analysis for different values of jamming/signal ratio (JSR), range and the distance between antennas is made. Moreover, amplitude and phase difference tolerance analysis for cross-eye angle deception technique used with range or velocity deception techniques is also analyzed.

K-distributed radar clutter sequence generator on FPGA

In this work, we present a sequence generator module on FPGA that provides the generation of K-distributed samples used in sea clutter modelling. Sequence generator is obtained by modification of widely used Box-Muller based Gaussian sequence generators into Rayleigh and Gamma sequence generators. The sqrt and ln functions in Box-Muller algorithm are approximated using piecewise polynomial function approximation method. The design implemented on a Xilinx Virtex-4 XC4VSX35- 12 FPGA can generate 5 million samples per second.

Implementation of a FPGA-based overlap-add filter

In this research, an efficient pipelined overlap-add filter is designed for the linear convolution of the streaming data. The designed filter uses the overlap-add method and modified radix- 4 architecture for the zero-padded input data. We used several techniques in order to decrease the hardware resources for the proposed design. Firstly, FFT (Fast Fourier Transform) resources are shared between the two FFT units used for the overlap-add method. Second, bit-reversed inputs are used for inverse FFT operation. The target device for the implementation is a Xilinx Virtex-5 FPGA. The architecture yields similar accuracy and throughput with the cost of less hardware resources than the designs using the commercial FFT IP(Intellectual Property) cores.