Mehmet İspir

Automated fixed-point precision optimization

An algorithm which minimizes the hardware resources of fixed-point operations for a given accuracy is presented. For range analysis, forward propagation is used in order to determine the ranges of the intermediate signals. For the precision analysis, a search algorithm is used. Analytical quantization error models are used with the precision search algorithm. The main novelty of this work is the use of the weighted search algorithm which can minimize the hardware resources for a specific FPGA. By using weights, the search algorithm is modified to produce an optimum result for the target FPGA for a specific hardware resource such as multipliers or blok rams.

Electronic attack techniques validation environment

In this article, the development of the electronic attack (EA) techniques validation environment is presented. EA techniques validation environment is a signal based closed hardware in loop which operates in intermediate frequency. By the development of this environment, radar and EA signals are processed on real time FPGA and the impact of radar and EA systems to each other are tested. Laboratory test environment provides cost/time advantage on both increasing the resistivity of radar systems to electronic attacks and the effectiveness of the electronic attack on the radar systems.

Implementation of Doppler noise jamming techniques using DRFM

In this paper, hardware implementation of Doppler noise and narrow band Doppler noise techniques those are jamming of Doppler frequency based on FPGA is explained. Pulse Doppler radar signal generator and receiver parts and algorithms of techniques are implemented on the Xilinx Virtex-4 FPGA. Besides, effective jamming to signal ratios of Doppler noise and narrow band Doppler noise techniques are compared.

Real-time multiple velocity false target generation in digital radio frequency memory

Real-time generation of multiple velocity false targets, which is an effective electronic counter measure (ECM) technique against pulse-doppler radar, is studied. Classical ECM techniques employ generation of velocity false targets by switching single signal source in time. This paper proposes a time and frequency domain generation approach, which is more flexible and efficient in terms of resource allocation for increased number of false targets. ECM technique is implemented in Xilinx Virtex-6 SX475t FPGA platform. Velocity false targets with different parameter sets are tested both in FPGA platform and computer environment. It is shown that the proposed technique is effective in false target generation and suitable for real time implementation requiring lower resource allocations compared to time and frequency domain generation.

Real-time time-frequency domain signal analysis for electronics support measure systems on FPGA

In this work, we have presented a real-time FPGA based electronic support measure processor detecting and identifying the signals in downconverted intermediate frequency band. The design is based on taking short time Fourier transform of the incoming signal to obtain a two dimensional gray scale image. The image is then binarized by using an adaptive binarization technique for signal detection and processed using image processing algorithms.

Min-max design of MTI filters with non-uniform pulse repetition intervals

In this work, design of non-uniform MTI filter for staggered MTI Radar systems is presented in the sense of min-max filter design. Corresponding design is studied to obtain the nearest improvement factor to the optimum MTI filter improvement factor. The performance of the design is examined with simulations and a detailed comparison with the non-uniform MTI filters in the literature is given.

Generation of clutter samples with different distributions and correlations

In this work, a new method recently proposed in the literature is investigated in terms of usability of generating radar clutter samples on FPGA. By using this method, clutter distribution and power spectrum density can be controlled independently and samples with desired characteristics can be obtained much easily. The usage of related method for generating clutter samples and details of the realized simulation that aims the FPGA implementation is presented with obtained results.

Channelizer structure in DRFM systems for real signals

In this paper, a channelized DRFM structure for DRFM(Digital Radio Frequency Memory) systems is presented. The novelty of this design is the modifications in the structure for supporting real signals without increasing the system delay. One of the most important parameters of a DRFMsystem is the system latency and the proposed architecture has less latency then the structures presented in the literature. The proposed architecture is implemented on a Virtex-6 SX475T and can run at 200 MHz clock speed.

K-distributed radar clutter sequence generator on FPGA

In this work, we present a sequence generator module on FPGA that provides the generation of K-distributed samples used in sea clutter modelling. Sequence generator is obtained by modification of widely used Box-Muller based Gaussian sequence generators into Rayleigh and Gamma sequence generators. The sqrt and ln functions in Box-Muller algorithm are approximated using piecewise polynomial function approximation method. The design implemented on a Xilinx Virtex-4 XC4VSX35- 12 FPGA can generate 5 million samples per second.

Implementation of a FPGA-based overlap-add filter

In this research, an efficient pipelined overlap-add filter is designed for the linear convolution of the streaming data. The designed filter uses the overlap-add method and modified radix- 4 architecture for the zero-padded input data. We used several techniques in order to decrease the hardware resources for the proposed design. Firstly, FFT (Fast Fourier Transform) resources are shared between the two FFT units used for the overlap-add method. Second, bit-reversed inputs are used for inverse FFT operation. The target device for the implementation is a Xilinx Virtex-5 FPGA. The architecture yields similar accuracy and throughput with the cost of less hardware resources than the designs using the commercial FFT IP(Intellectual Property) cores.