En-Jui Chang

Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip Systems

Network-on-chip systems can achieve higher performance than bus systems for chip multiprocessor systems. However, as the complexity of the network increases, the channel and switch congestion problems become major performance bottlenecks. An effective adaptive routing algorithm can help minimize path congestion through load balancing. However, conventional adaptive routing schemes only use channel-based information to detect the congestion status. Due to the lack of switch-based information, channel-based information is difficult to reveal the real congestion status along the routing path. Therefore, in this paper, we remodel the path congestion information to show hidden spatial congestion information and improve the effectiveness of routing path selection. We propose a path-congestion-aware adaptive routing (PCAR) scheme based on the following techniques: 1) a path-congestion-aware selection strategy that simultaneously considers switch congestion and channel congestion, and 2) a contention prediction technique that uses the rate of change in the buffer level to predict possible switch contention. The experimental results show that the proposed PCAR scheme can achieve a high saturation throughput with an improvement of 15.4%-48.7% compared to existing routing schemes. The proposed PCAR method also includes a VLSI architecture, which has higher area efficiency with an improvement of 16%-35.7% compared with the other router designs.

Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems

The regular topology of mesh-based network-on-chip (NoC) provides flexible and scalable architecture for chip multiprocessor (CMP) systems. However, as the complexity of network increases, routing problems become performance bottlenecks. In the field of wide area networks (WANs), ant colony optimization (ACO) has been applied to an adaptive routing for improving performance and achieving load balancing. Nevertheless, if we directly apply ACO to NoC systems, the implementation cost of ACO is excessively high. To overcome this problem, the ACO-based adaptive routing must be reformulated while considering both router cost and NoC efficiency. This work proposes the regional ACO-based cascaded adaptive routing (RACO-CAR) scheme with the following techniques: 1) table elimination by removing redundant information, 2) table sharing by grouping pheromone information to merge table content, and 3) cascaded routing that assigns traffic to different uncongested regions to balance traffic. Our experimental results demonstrate that the RACO-CAR scheme has an improvement of 3.9-36.84 percent in saturation throughput compared with existing adaptive routing schemes. The implementation cost of the RACO-CAR router is only 37.4 percent of that of the ACO-based router with full routing table. Therefore, the proposed RACO-CAR scheme has high area efficiency, defined as saturation throughput divided by the total cost of router.

Regional ACO-based routing for load-balancing in NoC systems

Ant Colony Optimization (ACO) is a problem-solving technique that was inspired by the related research on the behavior of real-world ant colony. In the domain of Network-on-chip (NoC), ACO-based adaptive routing has been applied to achieve load-balancing effectively with historical information. However, the cost of the ACO network pheromone table is too high, and this overhead grows fast with the scaling of NoC. In order to fix this problem, it is essential to model the ACO algorithm in more careful consideration of the system architecture, available hardware resource, and appropriate transformation from the ant colony metaphor. In this paper, we analyzed the NoC network characteristic and bring about the corresponding issues of implementing ACO on NoC. We proposed a Regional ACO-based routing (RACO) with static and dynamic regional table forming technique to reduce the cost of table, share pheromone information, and adopt look-ahead model for further load-balancing. The experimental results show that RACO can be implemented with less memory, less cost increase on scaling, and better performance of load-balancing compared to traditional ACO-based routing.

RC-Based Temperature Prediction Scheme for Proactive Dynamic Thermal Management in Throttle-Based 3D NoCs

The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in multicore systems using die stacking in recent days. Because of the larger power density and the heterogeneous thermal conductance in different silicon layers of 3D NoC, the thermal problems of 3D NoC become more exacerbated than that of 2D NoC and become a major design constraint for a high-performance system. To control the system temperature under a certain thermal limit, many Dynamic Thermal Managements (DTMs) have been proposed. Recently, for emergent cooling, the full throttling scheme is usually employed as the system temperature reaches the alarming level. Hence, the conventional reactive DTM suffers from significant performance impact because of the pessimistic reaction. In this paper, we propose a throttle-based proactive DTM(T-PDTM) scheme to predict the future temperature through a new Thermal RC-based temperature prediction (RCTP) model. The RCTP model can precisely predict the temperature with heterogeneous workload assignment with low constant computational complexity. Based on the predictive temperature, the proposed T-PDTM scheme will assign the suitable clock frequency for each node of the NoC system to perform early temperature control through power budget distribution. Based on the experimental results, compared with the conventional reactive throttled-based DTMs, the T-PDTM scheme can help to reduce 11.4~80.3 percent fully throttled nodes and improves the network throughput by around 1.5~211.8 percent.

ACO-based Cascaded Adaptive Routing for traffic balancing in NoC systems

Ant Colony Optimization (ACO) is a bio-inspired algorithm extensively applied in optimization problems. The performance of Network-on-Chip (NoC) is generally dominated by traffic distribution and routing. With more precise network information for path selection by using pheromone, ACO-based adaptive routing has higher potential to overcome the unbalance and unpredictable traffic load. On the other hand, the implementation cost of ACO is in general too high to store network information in pheromone memory, which is a routing table of all destination-channel pairs. We propose an ACO-based Cascaded Adaptive Routing (ACO-CAR) by combining two features: 1) table reforming by eliminating redundant information of far destinations from full routing table, and 2) adaptive searching of cascaded point for more precise network information. Our experimental results show that ACO-CAR has lower latency and higher saturation throughput, and can be implemented with 19.05% memory of full routing table.

Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems

The partially adaptive routing plays an important role in the performance of Network-on-Chip (NoC). It uses information of the network to select a better path to deliver a packet. However, it may have imbalanced path diversity in different directions, which makes their tolerances of traffic load differ a lot from each other. This characteristic would cause problems in traffic balancing but give us extra information of the network. To achieve load balancing, in this paper, we present an adaptive routing scenario with Path-Diversity-Aware (PDA) and Augmented-PDA (A-PDA) selections, which use the information of path diversity. Moreover, we derive a formula to quantify the characteristic of path diversity. Experiments with different scenarios were conducted. The simulation results show that our proposed selections have an advantage over other selection functions in saturation throughput, with up to 36.84%, and have better scalability in large scale NoC. In addition, a low-cost router architecture is proposed to implement PDA and A-PDA and the synthesized results are also shown in this paper.

Ant Colony Optimization-Based Adaptive Network-on-Chip Routing Framework Using Network Information Region

The network-on-chip (NoC) system can provide more scalable and flexible on-chip interconnection compared with system bus. The performance of on-chip adaptive routing algorithms greatly relies on the adopted network information. To the best our knowledge, previous routing algorithms utilize either spatial or temporal network information to improve performance. However, few works have established a framework on analyzing the network information nor showed how to integrate the spatial and temporal network information. In this paper, we define the network information region (NIR) framework for NoC systems. The NIR can indicate arbitrary combinations of network information and corresponding routing algorithms. We demonstrate how to apply NIR on analyzing the adaptive routing algorithms. To further demonstrate how NIR can help to integrate the spatial or temporal network information, we propose the ACO-based pheromone diffusion (ACO-PhD) adaptive routing framework based on the NIR. By diffusing the pheromone outward, spatial and temporal network information can be exchanged among adjacent routers. The range (i.e., size and shape) of the NIR is controllable by setting the parameters in the ACO-PhD algorithm. We show that we can reconfigure the ACO-PhD algorithm to each routing algorithm in its NIR subsets by adjusting the parameter settings. Finally, we implement and analyze the hardware design of corresponding router architecture. The results show an improvement of 4.86-16.93 percent on network performance and the highest area efficiency is achieved by the proposed algorithm.

Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems

Network-on-Chip (NoC) systems achieve higher performance than bus systems for chip multiprocessor (CMP) systems. However, as the complexity of network increases, routing problems become performance bottlenecks. Conventional routings only use local or regional buffer occupancy (BO) information to choose a better path to deliver a packet. Due to lack of path diversity (PD) information, which is global information, these routings are difficult to spread traffic to different paths for load balancing. Therefore, in this paper, we present a latency prediction model to simultaneously consider PD and BO information. Based on this model, this work proposes Hybrid Path-Diversity-Aware (Hybrid PDA) adaptive routing to overcome congestion problem in NoC. Experiments with different scenarios are conducted. The simulation results show that the proposed selection has a considerable latency reduction over other selection functions, with up to 94.6%, and has better scalability in large scale NoC.

Implementation of ACO-Based Selection with Backward-Ant Mechanism for Adaptive Routing in Network-on-Chip Systems

The Networks-on-Chip (NoC) provides regular and scalable design architecture for the chip multiprocessor (CMP) systems. The routing efficiency dominates the overall system performance because of more complex applications and network scaling. The Ant Colony Optimization (ACO) is a distributed collective-intelligence algorithm. The ACO-based selection scheme with Backward-Ant mechanism (ACO-BANT) can provide extra feedback congestion information compared with forward-ant mechanism. However, the storing and computation cost of BANT is too high for the NoC systems. In this work, we implement the ACO-BANT selection scheme with feasible cost on NoC. The simulation results show that the proposed scheme yields improvements in saturation throughput by 16.26% compared to the OBL selection. We also implement the router architecture of the proposed scheme, which has the highest improvement-to-overhead ratio.

Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems

Network-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With the increasing number of cores and the scaling of network in deep submicron (DSM) technology, the NoC systems become subject to manufacturing defects and have low production yield. Due to the fault issues, the reduction in the number of available routing paths for packet delivery may cause severe traffic congestion and even to a system crash. Therefore, the fault-tolerant routing algorithm is desired to maintain the correctness of system functionality. To overcome fault problems, conventional fault-tolerant routing algorithms employ fault information and buffer occupancy information of the local regions. However, the information only provides a limited view of traffic in the network, which still results in heavy traffic congestion. To achieve fault-resilient packet delivery and traffic balancing, this work proposes a Path-Diversity-Aware Fault-Tolerant Routing (PDA-FTR) algorithm, which simultaneously considers path diversity information and buffer information. Compared with other fault-tolerant routing algorithms, the proposed work can improve average saturation throughput by 175 percent with only 8.9 percent average area overhead and 7.1 percent average power overhead.