Engel Roza

Analog-to-digital conversion via duty-cycle modulation

An exchange of the amplitude axis for the time axis offers a possibility of overcoming resolution problems in analog-to-digital conversion in low-voltage CMOS circuits and/or of circumventing special resistor options in silicided processes. This exchange can be effected via some form of duty-cycle modulation. For its implementation a circuit configuration is described, consisting of an asynchronous sigma-delta modulator, followed by a phase-synchronized tapped ring oscillator which produces a poly-phase signal for sampling the asynchronous signal at a relatively low frequency. A detailed analysis is presented which accurately predicts the properties of the conversion scheme with respect to aliasing, quantization noise and nonlinear distortion. The results are illustrated with simulations of a design example.

Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer

Asynchronous sigma-delta modulators (ASDMs) are closed-loop nonlinear systems that transform the information in the amplitude of their input signal into time information in the output signal, without suffering from quantization noise such as in synchronous sigma-delta modulators. This is an important advantage with many interesting applications. In contrast with their synchronous counterparts, ASDMs have been underexposed. Both conceptually and analytically, they are quite complex. This paper investigates in detail the analysis, design and circuit-implementation aspects of ASDMs with a binary quantizer. In the ASDM, the amplitude-time transformation is done using an inherent self-oscillation denoted as a limit cycle. The oscillation frequency is addressed as the main design parameter that determines the spectral properties of the ASDMs and the quality of the amplitude-time transformation. Analytical and graphical derivations of the limit cycle frequency are treated. The impact of the filter order and the properties of the nonlinear element are elaborated on. Circuit implementations and the tradeoffs in the design are presented for a first- and a second-order ASDM that target the VDSL front-end specifications. Prototypes are implemented in a digital 0.18-/spl mu/m 1.8-V CMOS technology. The measured SFDR is 75dB in a frequency band of 8MHz for the first-order ASDM, and 72dB in a band of 12MHz for the second-order ASDM. The dissipated power is 1.5 mW and 2.2 mW, respectively.

Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission

An analysis is presented of the performance of phaselocked timing extraction circuits for baseband pulse code transmission. The phase error of the extracted timing wave is influenced by the properties of three essential stages in signal processing: prefiltering, nonlinear treatment, and narrow-band filtering. The analysis enables us to calculate quantitatively the quasi-static and the dynamic part of the phase error for arbitrary but specified types of signal processing. This is more than can be done with existing theory in the case of resonant-type timing extraction circuits. Examples are given for practical cases, and conditions for optimum performance are derived. Furthermore, the behavior of such phase-locked circuits in a chain of repeaters is investigated, and in particular, the propagation law for jitter. Byrnes model, as used for resonant-type timing extraction circuits, therefore is generalized. It is shown analytically and experimentally that by proper implementation of the timing extraction circuit, considerable improvement can be obtained as compared with resonant-type circuits.

A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption

This work describes a method for analysis of voltage-to-current converters (V-I converters or transconductors) and a novel V- I converter circuit with significantly improved linearity. The new circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third- and fifth-order harmonic distortion components in the transconductor characteristics. An evaluation of the optimal circuit dimensioning is shown. Simple and robust design rules are derived for the chosen operation conditions. The transistor implementation is presented and a prototype V- I converter is realized in a digital 0.18-/spl mu/m CMOS technology. The measured spurious-free dynamic range is 75 dB in a frequency band of 10 MHz. The circuit occupies less than 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.

Poly-phase sigma-delta modulation

A new circuit is described for the implementation of analog sigma-delta modulation. It is based upon the use of a poly-phase sampler with the aim of obtaining high over-sampling ratios at low clock frequencies. A detailed analysis of second-order systems is made to predict its performance. The basic modeling comprises the incorporation of sampling noise within limit cycle oscillations of the modulator. It is shown that the polyphase sigma-delta modulator can be conceived as an internally sampled asynchronous sigma-delta modulator. The theoretical model presupposes a low limit cycle frequency as compared with the effective sampling frequency. In spite of the fact that this condition is not met in the extreme of conventional single-phase sigma-delta modulation, the theoretical result obtained for this special case is close to the result obtained from the conventional sampled data model. Poly-phase sigma-delta modulation may therefore be regarded as a generalization of conventional single-phase sigma-delta modulation. The results of the theory are illustrated by simulation results of a practical design example.

An Experimental 560 Mbits/s Repeater with Integrated Circuits

The bandwidth penalty of digital systems is very obvious in the case of transmission over coaxial cables because of the exponential increse of cable attenuation with square root of frequency. From capacity point of view, it is only at very high information rates (> 500 Mbit/s typically) that a digital system might be competitive with an analog system, because the disadvantage of noise accumulation in an analog system ultimately cancels the bandwidth penalty of the digital system. In addition, it is, however, difficult to realize common functions, such as amplification, equalization, regeneration, clock extraction, etc. with electronic components having a frequency range comparable to the frequency range of the information signal, which extends from zero frequency to the microwave range. Besides, the complexity of a regenerative repeater should be kept to a minimum for reliability reasons. It is shown in the paper that with present-day technology a 560 Mbit/s repeater can be constructed, operating in sections of 1.5 km coaxial cable (2.6/9.5 mm). Also, we demonstrate that new technologies exist which may lead to repeaters with a high degree of monolithic integration, even at such a speed, which is important from the reliability viewpoint. The constructed and described repeater is characterized by unconventional and economic design of amplifier/equalizer and clock extractor and by monolithically integrated decision circuits.

Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption

This paper describes a method for analysis and design of MOS voltage-to-current converters (V-I converters or transconductors) and introduces a novel V-I converter circuit with significantly improved linearity performance. The proposed method uses harmonic compensation for the linearization of the V-I characteristics and introduces a normalized representation of the converter equations. The analysis is applied for several circuit topologies based on MOS differential pairs. The circuits are compared with respect to their current consumption, signal to noise ratio, achievable linearity and bandwidth. The minimum required current consumption for certain linearity and dynamic range is derived. The proposed novel V-I converter circuit uses a combination of local resistive feedback and cross-coupling. In this way, it achieves significant, simultaneous suppression of the third and the fifth order harmonic components in the transconductor output current. The implementation constraints and the performance of the new circuit solution are evaluated via simulations on transistor level. A standard digital 0.18 micrometer, 1.8V, CMOS process is used.

A Practical Design Approach to Decision Feedback Receivers with Conventional Filters

A method for designing conventional filters for decision feedback systems is described. Practical considerations, such as error propagation effect, timing inaccuracy and complexity, are incorporated in the design rules. In particular, non-band-limited noisy transmission channels and channels impaired by bandwidth limitation are investigated. In addition, noise and bandwidth limitations are taken into account simultaneously. The design approach is based upon polynomial descriptions which reveal simple relationships between the forward and feedback path, a stability measure which is representative of the error propagation, and an evaluation in terms of Laguerre polynomials. Results of simulations in hardware are given by way of a practical example and a binary regenerative transmission system for coaxial cables is studied.

Video-rate D/A converter using reduced rate sigma-delta modulation

Full 5-MHz-bandwidth video-signal is converted from digital-to-analog by a novel sigma-delta modulation technique at an equivalent PCM-precision of 8 bits. This new type of signal processing allows the sigma-delta modulator to operate at 54-MHz, which is about a quarter of the rate that would be required in equivalent conventional configurations. Owing to the reduced clock frequency, the power dissipation of the D/A converter is as low as 15 mW.

Recursive bitstream conversion: the reverse mode

Further results are presented of the recursive bit-stream conversion technique. In particular the sample rate conversion problem is studied to convert a low frequency bit parallel sequence with high word accuracy (such as a PCM signal) into a high frequency sequence with low word accuracy (ultimately to the 1-bit bit-stream format). It is shown that recursive bit-stream conversion is a generalization of a digital sigma-delta modulator or noise shaper. Two important advantages of recursive bit-stream conversion are emphasized. One of these is the property that upsampling and noise shaping are simultaneously performed, set that in theory separate upsampling filters are superfluous. It is shown that a modest performance penalty has to be paid for this property. The other advantage of recursive bit-stream conversion is its capability to perform the major part of the required signal processing at the lower frequency, rather than at the higher frequency as in conventional schemes. The developed theory has been verified with simulation examples. >