Sotir Filipov Ouzounov

A 2.75mW wideband correlation-based transceiver for body-coupled communication

Electronic devices in contact or in close proximity to the human body can use its conductive properties to establish body coupled communication (BCC) between each other. This human centric communication paradigm can be used for wireless body-area networks to reduce the impact of interference on/from RF systems, to avoid the fading effect that the body has on radio systems and to enable power efficient, high data-rate wireless links.

Sigma-delta modulators operating at a limit cycle

A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.

A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption

This work describes a method for analysis of voltage-to-current converters (V-I converters or transconductors) and a novel V- I converter circuit with significantly improved linearity. The new circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third- and fifth-order harmonic distortion components in the transconductor characteristics. An evaluation of the optimal circuit dimensioning is shown. Simple and robust design rules are derived for the chosen operation conditions. The transistor implementation is presented and a prototype V- I converter is realized in a digital 0.18-/spl mu/m CMOS technology. The measured spurious-free dynamic range is 75 dB in a frequency band of 10 MHz. The circuit occupies less than 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.

On the characterization of limit cycle modes in oversampled data converters

This paper studies the appearance of periodic and quazi-periodic modes, denoted as limit cycles, in the operation of closed-loop oversampled data converters. It demonstrates that the properties of these limit cycles are largely determined by the parameterization of the system loop filter, the amplitudes and the frequencies of the applied input signals, and the applied sampling frequency. For the analysis, quantization in amplitude and quantization in time are seen as separate functions. The quantizer is represented with sampled describing functions and a quazi-linear time-variant model for the loop operation is introduced and illustrated with simulation examples.

Limit cycle counting based smart background calibration of continuous time sigma delta ADCs

In this paper, a new background calibration technique for sigma delta modulators (SDMs) is presented. This method uses limit cycle analysis of SDMs as a theoretical base. Several non-idealities such as loop filter inaccuracy, excess loop delay and instability can be corrected using this technique. This method works in background by observing the bit-stream and generating limit cycle distributions during normal operation. It then uses the distribution data to estimate the non-idealities and takes steps to correct them. As a result, the proposed technique does not require any special test signals or customized hardware circuitry used in other calibration approaches. This technique can be used to calibrate the loop filter coefficients, delay and even hysteresis in the quantizer to obtain the required performance.

Automatic filter calibration for bandpass delta-sigma modulators

A bandpass delta-sigma modulator with a widely tunable center frequency range for direct digitization of IF or RF signals can be a key building block for highly digitized radio receivers. The performance of the bandpass modulator is highly dependent on the accuracy of the noise transfer function zero locations in the presence of process spread. An automatic calibration method is proposed to calibrate the noise transfer function zeros to their desired locations based on minimizing the variance of the decimated output bitstream of the modulator. The calibration does not need external test stimuli nor does it require complex hardware.

A Background Calibration Technique Based on Limit Cycles for Reconfigurable Sigma Delta Modulators

Reconfigurable ADCs bring a lot of functionality, high added value while sharing the development time and cost for each targeted application. Sigma Delta Modulators (SDMs) are very popular for their suitability for a wide range of applications. While individual SDMs can be tailored towards specific applications, a reconfigurable SDM addresses several of them at the same time. Due to their complexity (introduced by the programmability) and the limitations imposed by PVT variations, calibration is essential. To this effect, we introduce a new background calibration technique based on the limit cycle model of SDMs. We show how a simple counting and categorization of output bit-patterns can be used for measurement and correction/adjustment of the loop filter in the presence of multiple inaccuracies or changing operation conditions. The calibration scheme is demonstrated with measurement results from a test chip. The chip implements a third-order reconfigurable SDM for ultra-low bio-sensor current measurements. The reconfigurablity, coupled with the calibration scheme, allows a widely programmable bandwidth and dynamic range, making it useful for a variety of applications.

Frequency compensation in a two-integrator loop Gm-C biquad when realized with single stage OTAs

The paper considers the design of a two-integrator loop Gm-C second order filter, realized by single stage operational transconductance amplifiers (OTA). Two major problems are discussed: equalizing the maxima of OTA input voltages and unfavorable effect of OTA input capacitances. It is shown OTA input capacitances cause increasing of pole Q-factor and may turn the circuit to unstable. A method for avoiding of this problem is proposed, which could be applied for the other circuits of this class.

Higher-order DWA in bandpass delta-sigma modulators and its implementation

This paper proposes a simple implementation of a higher-order data weighted averaging algorithm to spectrally shape mismatch errors of a multi-bit D/A converter in a bandpass (BP) delta-sigma modulator. The proposed implementation avoids the need for a complex and slow sorting function that is usually associated with a higher-order DWA algorithm. An algorithm based on updating two pointers is used, similar as the widely used first-order DWA algorithm. The implementation is based on a pulse density modulated DAC that is clocked at a 3x higher rate compared to the delta-sigma modulator clock to accurately implement the 1x and 3x weight factors that are required by the algorithm. The implementation can also be used in a generalized bandpass DWA algorithm that can be easily adjusted to tune the noise-shaping characteristic to different center frequencies.

Bitstream switching rate based calibration of delta-sigma modulators

This paper proposes a simple and effective criterion based on the switching rate of the output bit-stream of a delta-sigma modulator to estimate the performance and stability of the modulator. The switching rate and its relation to the NTF design are analyzed for both single and multi-bit delta-sigma modulators as well as lowpass and bandpass modulators. A calibration method is proposed using the switching rate as calibration parameter to adjust non-idealities such as loopfilter zero spread and excess loop delay. The loopfilter coefficients can be adjusted to calibrate the delta-sigma modulator back to the specification by comparing the measured switching rate with the desired design criterion. The proposed technique is based only on counting and requires no external stimuli or complex hardware. The switching rate is a very simple performance indicator for testing of a delta-sigma modulator without the need for an FFT, as well as a powerful input parameter for calibration.