Eric A. G. Webster

Scaleable Single-Photon Avalanche Diode Structures in Nanometer CMOS Technology

Single-photon avalanche photodiodes (SPADs) operating in Geiger mode offer exceptional time resolution and optical sensitivity. Implementation in modern nanometer-scale complementary metal-oxide-semiconductor (CMOS) technologies to create dense high-resolution arrays requires a device structure that is scaleable down to a few micrometers. A family of three SPAD structures with sub-100-Hz mean dark count rate (DCR) is proposed in 130-nm CMOS image sensor technology. Based on a novel retrograde buried n-well guard ring, these detectors are shown to readily scale from 32 to 2 μm with improving DCR, jitter, and yield. One of these detectors is compatible with standard triple-well digital CMOS, and the others bring the first low-DCR realizations at the 130-nm node of shallow-trench-isolation-bounded and enhancement SPADs.

A Single-Photon Avalanche Diode in 90-nm CMOS Imaging Technology With 44% Photon Detection Efficiency at 690 nm

A CMOS and back-side illumination-compatible single-photon avalanche diode (SPAD) is reported in 90-nm imaging technology with a peak photon detection efficiency of ≈ 44% at 690 nm and better than ≈20% at 850 nm. This represents an approximately eightfold improvement in near infrared sensitivity over existing CMOS SPADs. This result has important implications for optical communications, time-of-flight ranging, and optical tomography applications. The 6.4-μm-diameter SPAD also achieves the following: low dark count rates of ≈100 Hz with ≈51-ps FWHM timing resolution and a low after-pulsing probability of ≈0.375%.

A High-Performance Single-Photon Avalanche Diode in 130-nm CMOS Imaging Technology

A single-photon avalanche diode (SPAD) is reported in a 130-nm CMOS imaging process which achieves a peak photon detection efficiency (PDE) of ≈72% at 560 nm with >; 40% PDE from 410 to 760 nm. This is achieved by eliminating junction isolation, utilizing dielectric stack optimizations designed for CMOS imaging, and operating at high bias enabled by ac coupling. The 8-μm-diameter device achieves a low median dark count rate of 18 Hz at 2-V excess bias (VEB), a <; 60-ps FWHM timing resolution at 654 nm from VEB = 6 V to VEB = 12 V, and a <; 4% after-pulsing probability. This represents performance which is comparable to fully customized discrete SPADs.

Transient Single-Photon Avalanche Diode Operation, Minority Carrier Effects, and Bipolar Latch Up

The operation of planar CMOS single-photon avalanche diodes (SPADs) is studied with the use of transient technology-computer-aided-design simulations calibrated with measured results. The SPADs transient I-V curve is reported and is found to have negative differential resistance behavior that is unlike steady state. The quenching process is discussed with reference to power supply decoupling. It is found that minority carriers involved in SPAD breakdown play an important role in device performance and provide insight into a trapless after-pulsing mechanism. The influence of the parasitic bipolar transistor present in planar SPADs is analyzed. The bipolar is found to be responsible for a SPAD latch-up failure mechanism and potentially additional after pulsing. Design methods and bias possibilities for mitigating the influence of the parasitic bipolar are discussed.

Per-Pixel Dark Current Spectroscopy Measurement and Analysis in CMOS Image Sensors

A per-pixel dark current spectroscopy measurement and analysis technique for identifying deep-level traps in CMOS imagers is presented. The short integration time transfer gate subtraction experimental technique used to obtain accurate results is described and discussed. The activation energies obtained for molybdenum (≈0.3 eV), tungsten (≈0.37 eV), and the phosphorus-vacancy (E-center) (≈0.44 eV) trap levels in silicon match published results measured with other techniques. The Meyer-Neldel Relationship (MNR) was observed between the Arrhenius preexponential frequency factor and activation energy. The trap capture cross-sectional calculation methodology using the MNR is presented. The cross sections of molybdenum, tungsten, and the E-center were calculated as ≈1 × 10-16 cm2, ≈1.5 × 10-16 cm2, and ≈2.5 × 10-16 cm2, respectively, at 318 K. The data obtained suggest electric field enhanced emission, and Poole-Frenkel barrier force lowering of E-center defects occurs in the pinning implant regions. It is proposed that a changing Fermi level results in the correct activation energies being obtained below half the band gap and that the dark current measurement process is affected by the measurement time result of statistical mechanics. It is also tentatively suggested that, in this case, the observed MNR is a geometric relationship and not due to a physical process.

A silicon photomultiplier with >30% detection efficiency from 450–750nm and 11.6μm pitch NMOS-only pixel with 21.6% fill factor in 130nm CMOS

A 16×16 Silicon Photomultiplier (SiPM) is reported in a 130nm CMOS imaging technology with a photon detection probability of >;30% from 450-750nm. The SiPM demonstrates a 21.6% fill factor with an 11.6μm pitch and 8μm diameter SinglePhoton Avalanche Diodes (SPADs). This is achieved using a new SPAD structure with integrated resistor and capacitor. NMOS-only pixel electronics are used to improve fill factor and to implement an addressable array of SPADs that are isolated from the array and column load. A 1T DRAM in each pixel is implemented to inhibit the output of high dark count rate (DCR) SPADs. The SiPM also achieves: a median DCR of ≈200Hz at 1.2V excess bias; low after pulsing; and a SPAD timing jitter of ≈95ps at 654nm with a column delay of ≈100-200ps.

A TCAD and Spectroscopy Study of Dark Count Mechanisms in Single-Photon Avalanche Diodes

It is shown through dark count rate spectroscopy (DCRS) and TCAD-simulations that in single-photon avalanche diodes (SPADs), the majority of low dark count rate (DCR) devices in modern CMOS arrays are free of deep-level traps and that DCR can therefore be explained by saturation current and band-to-band tunneling (BTBT). The DCRS performed on the Megaframe 32 × 32 show that the activation energies for the high DCR devices are consistent with a single type of defect at ≈ 0.44 eV, thought to be the E-center, in differing electric fields. Calibrated TCAD-simulated reverse bias leakage currents are orders of magnitude lower than those measured due to the lack of parasitic leakage paths but give theoretical DCRS that are close to the measured values for four different SPAD designs and predict the voltage dependence at high fields. The coefficients for Kanes indirect tunneling model in the [100] direction are determined as A ≈ 2×1015 cm-3/s and B ≈ 2.39×107 V/cm through TCAD calibration, DCR measurement, and theory. It is found that indirect BTBT dominates the DCR of SPADs with low breakdown voltages.

High fill factor digital Silicon Photomultiplier structures in 130nm CMOS imaging technology

This paper discusses recent progress in the realization of fully digital Silicon Photomultipliers (SiPMs) in an advanced 130nm CMOS imaging process. A dedicated electrical/optical crosstalk characterization chip is reported, featuring a 16×16 SPAD SiPM with on-chip quench, SPAD enable/disable and readout circuitry positioned outside the SPAD array. Recent advances in well sharing are employed to deliver a fill factor of 38%. Integral crosstalk of <;2% was measured between a SPAD and its neighbors - the lowest yet reported for a high fill factor SiPM structure - measured using parallel readout channels allowing adjacent SPAD waveforms to be monitored in real time.

A 2um diameter, 9hz dark count, single photon avalanche diode in 130nm cmos technology

We report a CMOS single photon avalanche diode (SPAD) with a 2um active diameter, 9Hz dark count rate at 20°C, photon detection efficiency peak of 14% at 500nm, implemented in a 130nm process technology. The implicit guard ring structure relies on retrograde well doping and overcomes a key problem in scaling SPAD devices to small dimensions. TCAD-based device simulations point the way to high resolution, high fill-factor single photon imaging.

A Dual-Junction Single-Photon Avalanche Diode in 130-nm CMOS Technology

A dual-junction single-photon avalanche diode structure is reported in a 130-nm low-voltage CMOS technology. The device comprises two stacked avalanche multiplication regions with virtual guard ring constructions. An 8.6- μm-diameter p-well is placed within a 12.3- μm-diameter deep n-well. At 3-V excess bias, the junctions operate with median dark count rates of 10 and 5 kHz and photon detection efficiencies of 32% at 450 nm and 29% at 670 nm, respectively. We demonstrate that the junction at which a photon is detected can be uniquely distinguished by the dead time of the Geiger mode pulse allowing spectral discrimination by simple digital circuitry.