Eric Andre

A 1.2-V dual-mode WCDMA/GPRS /spl Sigma//spl Delta/ modulator

A dual-mode /spl Sigma//spl Delta/ modulator is designed to meet the specifications of a WCDMA/GPRS receiver and is composed of a single-bit second-order modulator followed by a multi-bit stage that adapts performance to broadband signals. The modulator achieves 82dB and 70dB of dynamic range over bandwidths of 100kHz and 1.92MHz, respectively, and dissipates 4.3mW from a 1.2V supply. The circuit is implemented in 0.13/spl mu/m CMOS technology and occupies an active area of 0.2mm/sup 2/.

A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS

A low-power 1.2 V pipelined ADC is implemented in a 65 nm CMOS process to achieve 10b resolution at 100 MS/s based on the use of a dedicated thin-oxide high-performance analog (HPA) MOS transistor. The pipeline ADC is composed of eight 1.5b pipelined stages followed by a 2b flash converter as the last stage. In order to optimize the power consumption, the capacitances and the bias current of each stage have been scaled down along the pipeline chain. Measurement results of this ADC revealed a SNDR of 59 dB with a power dissipation of 4.5 mW. The core occupies 0.07 mm2, and 0.1 mm2 with the reference.

A 120nm low power asynchronous ADC

This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an asynchronous analog-to-digital converter (A-ADC) is tackled. Its principle is based on a nonuniform sampling scheme and asynchronous technology that allow significant activity and power savings. A test chip targetting 10-bit speech applications has been fabricated using the 120nm CMOS process from STMicroelectronics. The power consumption is lower than 180/spl mu/W leading to a figure of merit two times better than those of classical Nyquist converters recently published.

A 0.12 /spl mu/m CMOS DVB-T tuner

A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration with a digital demodulator IP.

Analog bandwidth mismatch compensation for time-interleaved ADCs using FD-SOI technology

This paper introduces an analog bandwidth mismatch compensation technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs). It takes advantage of a Fully Depleted Silicon On Insulator (FD-SOI) technology to compensate for the bandwidth mismatch errors among channels. Our technique utilizes the body-effect to adjust the on-resistance of the sampling switch, by means of a 6-bit Digital-to-Analog-Converter (DAC). Simulations of a 2-channel TI-ADC running at fs= 4GHz shows the effectiveness of the correction. The spurious-free dynamic range (SFDR) is improved from 44.63 dB to 83.12 dB for a sine-wave just below the Nyquist frequency(fNyquist) of 2 GHz.

A new analytical approach of the impact of jitter on continuous time delta sigma converters

The performances of continuous time delta sigma converters are severely affected by clock jitter and no generic technique to predict the corresponding degradations is nowadays available. This paper presents a new analytical approach to quantify the power spectral density of jitter errors. This generic computational method can be applied to all kind of delta sigma converters. Furthermore, clock imperfections are described by means of phase noise spectrum, consequently all possible type of jitters can be taken into account. This paper also describes the temporal non ideal clock models that have been created to simulate the impact of jitter on delta sigma converters and validate the theoretical results.