Frederic Paillardet

A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS

A low-power 1.2 V pipelined ADC is implemented in a 65 nm CMOS process to achieve 10b resolution at 100 MS/s based on the use of a dedicated thin-oxide high-performance analog (HPA) MOS transistor. The pipeline ADC is composed of eight 1.5b pipelined stages followed by a 2b flash converter as the last stage. In order to optimize the power consumption, the capacitances and the bias current of each stage have been scaled down along the pipeline chain. Measurement results of this ADC revealed a SNDR of 59 dB with a power dissipation of 4.5 mW. The core occupies 0.07 mm2, and 0.1 mm2 with the reference.

A 0.12 /spl mu/m CMOS DVB-T tuner

A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration with a digital demodulator IP.

Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS

A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.

Embeddable CMOS 3.3 V analog front end for CD applications

Increasingly, the consumer CD market requires low cost integrated circuits. An embeddable pure CMOS analog front-end including photodiode preamplifiers has been developed in 0.5 /spl mu/m technology for the CD one chip approach. >

A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS

This paper describes a fully integrated scalable discrete-time receiver based on a merged SC mixer, filter and SAR ADC meeting the requirements of IEEE 802.16e and 802.11b/g/n standards. Recent work has shown the use of SC-filtering techniques in radio receivers, where sampling is done early in the RX path. Such discrete-time architectures require an early anti-aliasing (AA) filter prior to sampling. Multiple AA and channel filters with decimation stages have been used to strongly attenuate alias and adjacent channels and to allow sampling of the signal at a reasonable rate at the ADC stage.IF amplifiers are necessary to drive ADC input stage. The direct-conversion receiver architecture proposed here is based on a fully-passive CMOS approach. It is composed of one transconductance LNA and a resistive attenuator.

A complete single-chip front-end for digital satellite broadcasting

This paper presents a single-chip integrating an RF tuner, a demodulator and channel decoder for digital satellite applications. The outstanding achievement is the integration of the zero IF and the demodulation on a standard 0.18 /spl mu/m CMOS process.