John F. Shelton

Fast multiple-word accesses from a multi-way set-associative cache memory

Method and apparatus for checking cache coherency in a computer architecture

Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer

Apparatus for generation of scan control signals for initialization and diagnosis of circuitry in a computer

Multiple arbitration scheme

Computing system with a cache memory and an additional look-aside cache memory

Apparatus and method for operating chips synchronously at speeds exceeding the bus speed

Means for fast instruction decoding for a computer

Programmable rate generator

Double cache snoop mechanism.