Eric E. Retter

Combined DRAM and logic chip for massively parallel systems

A new 5 V 0.8 /spl mu/m CMOS technology merges 100 K custom circuits and 4.5 Mb DRAM onto a single die that supports both high density memory and significant computing logic. One of the first chips built with this technology implements a unique Processor-In-Memory (PIM) computer architecture termed EXECUBE and has 8 separate 25 MHz CPU macros and 16 separate 32 K/spl times/9 b DRAM macros on a single die. These macros are organized together to provide a single part type for scaleable massively parallel processing applications, particularly embedded ones where minimal glue logic is desired. Each chip delivers 50 Mips of performance at 2.7 W. This paper overviews the basic chip technology and organization some projections on the future of EXECUBE-like PIM chips, and finally some lessons to be learned as to why this technology should radically affect the way we ought think about computer architecture.

A parallel processing chip with embedded DRAM macros

A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology merges 100-K gate custom logic circuits and 4.5-Mb DRAM onto a 14.7/spl times/14.7 mm/sup 2/ die. The DRAM design is based on a 32-K/spl times/9-b (288-Kb) self-consistent macro form. It has independent address inputs, data I/O ports, access control circuits, and redundancy fuses and elements. The logic part of the chip consists of eight 16-b CPUs and some broadcast logic circuits. Each CPU and two DRAM macros (64-KB) comprise a processing element (PE), and hypercube connections among eight PEs are made for the scalable MPP capability. Each chip delivers 50-MIPS of performance at 2.7 W.