Eric M. Vogel

Large-Area Graphene Single Crystals Grown by Low-Pressure Chemical Vapor Deposition of Methane on Copper

Graphene single crystals with dimensions of up to 0.5 mm on a side were grown by low-pressure chemical vapor deposition in copper-foil enclosures using methane as a precursor. Low-energy electron microscopy analysis showed that the large graphene domains had a single crystallographic orientation, with an occasional domain having two orientations. Raman spectroscopy revealed the graphene single crystals to be uniform monolayers with a low D-band intensity. The electron mobility of graphene films extracted from field-effect transistor measurements was found to be higher than 4000 cm(2) V(-1) s(-1) at room temperature.

Graphene Films with Large Domain Size by a Two-Step Chemical Vapor Deposition Process

The fundamental properties of graphene are making it an attractive material for a wide variety of applications. Various techniques have been developed to produce graphene and recently we discovered the synthesis of large area graphene by chemical vapor deposition (CVD) of methane on Cu foils. We also showed that graphene growth on Cu is a surface-mediated process and the films were polycrystalline with domains having an area of tens of square micrometers. In this paper, we report on the effect of growth parameters such as temperature, and methane flow rate and partial pressure on the growth rate, domain size, and surface coverage of graphene as determined by Raman spectroscopy, and transmission and scanning electron microscopy. On the basis of the results, we developed a two-step CVD process to synthesize graphene films with domains having an area of hundreds of square micrometers. Scanning electron microscopy and Raman spectroscopy clearly show an increase in domain size by changing the growth parameters. Transmission electron microscopy further shows that the domains are crystallographically rotated with respect to each other with a range of angles from about 13 to nearly 30°. Electrical transport measurements performed on back-gated FETs show that overall films with larger domains tend to have higher carrier mobility up to about 16,000 cm(2) V(-1) s(-1) at room temperature.

The effect of chemical residues on the physical and electrical properties of chemical vapor deposited graphene transferred to SiO2

The effects of residues introduced during the transfer of chemical vapor deposited graphene from a Cu substrate to an insulating (SiO2) substrate on the physical and electrical of the transferred graphene are studied. X-ray photoelectron spectroscopy and atomic force microscopy show that this residue can be substantially reduced by annealing in vacuum. The impact of the removal of poly(methyl methacrylate) residue on the electrical properties of graphene field effect devices is demonstrated, including a nearly 2 × increase in average mobility from 1400 to 2700 cm2/Vs. The electrical results are compared with graphene doping measurements by Raman spectroscopy.

GaAs interfacial self-cleaning by atomic layer deposition

The reduction and removal of surface oxides from GaAs substrates by atomic layer deposition (ALD) of Al2O3 and HfO2 are studied using in situ monochromatic x-ray photoelectron spectroscopy. Using the combination of in situ deposition and analysis techniques, the interfacial “self-cleaning” is shown to be oxidation state dependent as well as metal organic precursor dependent. Thermodynamics, charge balance, and oxygen coordination drive the removal of certain species of surface oxides while allowing others to remain. These factors suggest proper selection of surface treatments and ALD precursors can result in selective interfacial bonding arrangements.

Detection of Ga suboxides and their impact on III-V passivation and Fermi-level pinning

The passivation of interface states remains an important problem for III-V based semiconductor devices. The role of the most stable bound native oxides GaOx (0.5≤x≤1.5) is of particular interest. Using monochromatic x-ray photoelectron spectroscopy in conjunction with controlled GaAs(100) and InGaAs(100) surfaces, a stable suboxide (Ga2O) bond is detected at the interface but does not appear to be detrimental to device characteristics. In contrast, the removal of the Ga 3+ oxidation state (Ga2O3) is shown to result in the reduction of frequency dispersion in capacitors and greatly improved performance in III-V based devices.

Contact resistance in few and multilayer graphene devices

The contact resistance of metals on backgated graphene field-effect transistors is studied. The residual resistance obtained at high backgate voltage is found to be in excellent agreement with the extracted values of contact resistance from transfer length measurements on graphene flakes. The contact resistance is found to be a significant contributor to the total resistance of graphene-based devices. The specific contact resistance is shown to be independent of the applied backgate voltage and the number of graphene layers.

First-principles study of metal-graphene interfaces

Metal-graphene contact is a key interface in graphene-based device applications, and it is known that two types of interfaces are formed between metal and graphene. In this paper, we apply first-principles calculations to twelve metal-graphene interfaces and investigate the detailed interface atomic and electronic structures of physisorption and chemisorption interfaces. For physisorption interfaces (Ag, Al, Cu, Cd, Ir, Pt, and Au), Fermi level pinning and Pauli-exclusion-induced energy-level shifts are shown to be two primary factors determining graphene’s doping types and densities. For chemisorption interfaces (Ni, Co, Ru, Pd, and Ti), the combination of Pauli-exclusion-induced energy-level shifts and hybridized states’ repulsive interactions lead to a band gap opening with metallic gap states. For practical applications, we show that external electric field can be used to modulate graphene’s energy-levels and the corresponding control of doping or energy range of hybridization.

Conformal Al2O3 dielectric layer deposited by atomic layer deposition for graphene-based nanoelectronics

We present a facile route which combines the functionalization of a highly oriented pyrolytic graphite surface with an atomic layer deposition (ALD) process to allow for conformal Al2O3 layers. While the trimethylaluminum (TMA)∕H2O process caused selective deposition only along step edges, the TMA∕O3 process began to provide nucleation sites on the basal planes of the surface. O3 pretreatment, immediately followed by the ALD process with TMA∕O3 chemistry, formed Al2O3 layers without any preferential deposition at the step edges. This is attributed to functionalization of graphene by ozone treatment, imparting a hydrophilic character which is desirable for ALD deposition.

Reducing extrinsic performance-limiting factors in graphene grown by chemical vapor deposition

Field-effect transistors fabricated on graphene grown by chemical vapor deposition (CVD) often exhibit large hysteresis accompanied by low mobility, high positive backgate voltage corresponding to the minimum conductivity point (V(min)), and high intrinsic carrier concentration (n(0)). In this report, we show that the mobility reported to date for CVD graphene devices on SiO(2) is limited by trapped water between the graphene and SiO(2) substrate, impurities introduced during the transfer process and adsorbates acquired from the ambient. We systematically study the origin of the scattering impurities and report on a process which achieves the highest mobility (μ) reported to date on large-area devices for CVD graphene on SiO(2): maximum mobility (μ(max)) of 7800 cm(2)/(V·s) measured at room temperature and 12,700 cm(2)/(V·s) at 77 K. These mobility values are close to those reported for exfoliated graphene on SiO(2) and can be obtained through the careful control of device fabrication steps including minimizing resist residue and non-aqueous transfer combined with annealing. It is also observed that CVD graphene is prone to adsorption of atmospheric species, and annealing at elevated temperature in vacuum helps remove these species.

Technology and metrology of new electronic materials and devices

Scaling of the metal oxide semiconductor (MOS) field-effect transistor has been the basis of the semiconductor industry for nearly 30 years. Traditional materials have been pushed to their limits, which means that entirely new materials (such as high-kappa gate dielectrics and metal gate electrodes), and new device structures are required. These materials and structures will probably allow MOS devices to remain competitive for at least another ten years. Beyond this timeframe, entirely new device structures (such as nanowire or molecular devices) and computational paradigms will almost certainly be needed to improve performance. The development of new nanoscale electronic devices and materials places increasingly stringent requirements on metrology.