Curt A. Richter

Contact-induced crystallinity for high-performance soluble acene-based transistors and circuits

The use of organic materials presents a tremendous opportunity to significantly impact the functionality and pervasiveness of large-area electronics. Commercialization of this technology requires reduction in manufacturing costs by exploiting inexpensive low-temperature deposition and patterning techniques, which typically lead to lower device performance. We report a low-cost approach to control the microstructure of solution-cast acene-based organic thin films through modification of interfacial chemistry. Chemically and selectively tailoring the source/drain contact interface is a novel route to initiating the crystallization of soluble organic semiconductors, leading to the growth on opposing contacts of crystalline films that extend into the transistor channel. This selective crystallization enables us to fabricate high-performance organic thin-film transistors and circuits, and to deterministically study the influence of the microstructure on the device characteristics. By connecting device fabrication to molecular design, we demonstrate that rapid film processing under ambient room conditions and high performance are not mutually exclusive.

A Flexible Solution-Processed Memristor

A rewriteable low-power operation nonvolatile physically flexible memristor device is demonstrated. The active component of the device is inexpensively fabricated at room temperature by spinning a TiO2 sol gel on a commercially available polymer sheet. The device exhibits memory behavior consistent with a memristor, demonstrates an on/off ratio greater than 10 000 : 1, is nonvolatile for over 1.2 times 106 s, requires less than 10 V, and is still operational after being physically flexed more than 4000 times.

Spectroscopic ellipsometry characterization of high-k dielectric HfO2 thin films and the high-temperature annealing effects on their optical properties

The optical properties of a set of high-k dielectric HfO2 films annealed at various high temperatures were determined by spectroscopic ellipsometry. The results show that the characteristics of the dielectric functions of these films are strongly affected by high temperature annealing. For a sample annealed at 600 °C, the film becomes polycrystalline, and its dielectric function displays a distinctive peak at 5.9 eV. On the other hand, the film remains amorphous without the 5.9 eV feature after 500 °C annealing. To model the dielectric functions, the Tauc–Lorentz dispersion was successfully adopted for these amorphous and polycrystalline films. The absorption edge was observed to shift to a higher energy at a high temperature annealing. Defects in the films were shown to relate to the appearance of a band tail above the absorption edge, and they appear to diminish with high temperature annealing.

Limitations of conductance to the measurement of the interface state density of MOS capacitors with tunneling gate dielectrics

A systematic study of the uncertainties, sensitivity and limitations of the conductance technique for extracting the interface state density of tunneling dielectrics is presented. The methodology required to extract device parameters and interface state density from conductance and capacitance data is reviewed and analyzed. The effect of uncertainties in device parameters on extracted interface state density was determined using experimental results of thin oxides (1.4 nm and 2.0 nm). Modeling was used to indicate the effects of various device parameters on the sensitivity of conductance to changes in interface state density. The effect of uncertainties in insulator capacitance of equivalently thin dielectrics on uncertainties in extracted interface state density is minimal. The effect of uncertainties in series resistance increases with increasing bias towards accumulation. An increase in the series resistance of the device causes reduced sensitivity to changes in interface state density especially for interface states located nearer the majority band edge; increasing tunneling current causes increased uncertainties and reduced sensitivity to changes in interface state density especially for interface states nearer midgap.

Ultraviolet/ozone treatment to reduce metal-graphene contact resistance

We report reduced contact resistance of single-layer graphene devices by using ultraviolet ozone treatment to modify the metal/graphene contact interface. The devices were fabricated from mechanically transferred, chemical vapor deposition grown single layer graphene. Ultraviolet ozone treatment of graphene in the contact regions as defined by photolithography and prior to metal deposition was found to reduce interface contamination originating from incomplete removal of poly(methyl-methacrylate) and photoresist. Our control experiment shows that exposure times up to 10 min did not introduce significant disorder in the graphene as characterized by Raman spectroscopy. By using the described approach, contact resistance of less than 200 Ω μm was achieved for 25 min ultraviolet ozone treatment, while not significantly altering the electrical properties of the graphene channel region of devices.

A comparison of quantum-mechanical capacitance-voltage simulators

We have systematically compared the results of an extensive ensemble of the most advanced available quantum-mechanical capacitance-voltage (C-V) simulation and analysis packages for a range of metal-oxide-semiconductor device parameters. While all have similar trends accounting for polysilicon depletion and quantum-mechanical confinement, quantitatively, there is a difference of up to 20% in the calculated accumulation capacitance for devices with ultrathin gate dielectrics. This discrepancy leads to large inaccuracies in the values of dielectric thickness extracted from capacitance measurements and illustrates the importance of consistency during C-V analysis and the need to fully report how such analysis is done.

Low frequency noise characterizations of ZnO nanowire field effect transistors

We fabricated ZnO nanowire field effect transistors (FETs) and systematically characterized their low frequency (f) noise properties. The obtained noise power spectra showed a classical 1∕f dependence. A Hooge’s constant of 5×10−3 was estimated from the gate dependence of the noise amplitude. This value is within the range reported for complementary metal-oxide semiconductor (CMOS) FETs with high-k dielectrics, supporting the concept that nanowires can be utilized for future beyond-CMOS electronic applications from the point of view of device noise properties. ZnO FETs measured in a dry O2 environment displayed elevated noise levels that can be attributed to increased fluctuations associated with O2− on the nanowire surfaces.

Silicon nanowire electromechanical switches for logic device application

We report the fabrication and characterization of nanowire electromechanical switches consisting of chemical-vapour-deposition-grown silicon nanowires suspended over metal electrodes. The devices operate as transistors with the suspended part of the nanowire bent to touch metal electrodes via electromechanical force by applying voltage. The reversible switching, large on/off current ratio, small subthreshold slope and low switching energy compared to current CMOSFET make the switches very attractive for logic device application. In addition, we have developed a physical model to investigate the switching characteristics and extract the material properties.

Silicon nanowire on oxide/nitride/oxide for memory application

We report the fabrication and characterization of Si nanowire memory devices with oxide/nitride/oxide stacked layers as the gate dielectrics and charge storage media. The devices were fabricated by using photolithography to pattern the metal contacts to the Si nanowires grown on pre-defined locations. A large memory window with high on/off-state current ratio due to the small radius and intrinsic doping of the Si nanowire is obtained. In addition, the simple reversible write/read/erase operations have been implemented with these memory devices. The dynamics of the nanowire/nitride charge exchange and its effect on the threshold voltage and memory retention have been investigated.

Precise Alignment of Single Nanowires and Fabrication of Nanoelectromechanical Switch and Other Test Structures

The integration of nanowires and nanotubes into electrical test structures to investigate their nanoelectronic transport properties is a significant challenge. Here, we present a single nanowire manipulation system to precisely maneuver and align individual nanowires. We show that a single nanowire can be picked up and transferred to a predefined location by electrostatic force. Compatible fabrication processes have been developed to simultaneously pattern multiple aligned nanowires by using one level of photolithography. In addition, we have fabricated and characterized representative devices and test structures including nanoelectromechanical switches with large on/off current ratios, bottom-gated silicon nanowire field-effect transistors, and both transfer-length-method and Kelvin test structures