Eric Naviasky

An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

This paper describes a low jitter phase-locked-loop (PLL) with a 4/sup th/ order control path, and a dual control voltage ring oscillator. Near constant voltage controlled oscillator (VCO) gain over process variations, in addition to compensation for feedback ratio variation, allows improved control of the PLL bandwidth. The PLL exhibits improved noise immunity with a wide (5:1) VCO frequency range, without the need for band switching or calibration routines. This PLL is fabricated in a 0.18 /spl mu/m CMOS logic process and exhibits <4 ps rms accumulated jitter.

An energy-efficient ring-oscillator digital PLL

A linear but fully digital phase control path and a bang-bang frequency control path enable an energy-efficient digital ring-oscillator PLL architecture. A 65nm CMOS prototype occupies 150µm × 170µm of area and generates a 3GHz clock from a 300MHz reference with 1.13ps rms period jitter while consuming 2mW from a single 1V power supply.

An improved wideband PLL with adaptive frequency response that tracks the reference

This paper describes a self-tuning 3/sup rd/ order type III phase-locked-loop (PLL) with the frequency control implemented in 3 parallel paths. The crucial elements that allow frequency response tracking are a triple control voltage controlled oscillator (VCO), a frequency to current (F2I) converter, and a switched capacitor loop filter. Near constant VCO gain over process variations, in addition to compensation for feedback ratio variation, near constant F2I gain over process variations and switched cap filters synchronized to the reference allows tailoring the open loop frequency response to track the reference. A high speed locking technique is employed which significantly reduces acquisition time in low bandwidth cases. This PLL was fabricated in a 0.18/spl mu/m CMOS logic process.

A 12-b 56MS/s pipelined ADC in 65nm CMOS

This paper describes a 1.2V, 12-b pipelined ADC implemented in a 65nm CMOS process. The circuit design techniques used to obtain high gain operational amplifiers in a deep-submicron process are described. A novel top-level simulation methodology is used to quantify the transient errors in each subrange stage, allowing their optimal design. The circuit employs various techniques for power reduction: class A-B op-amps, improved reference design, and frequency-to-current biasing.

A low-voltage low-power sigma-delta modulator with improved performance in overload condition

A 4/sup th/-order sigma-delta modulator is presented that offers significantly improved stability and SNR when the input is overloaded, compared to conventional single-bit modulators. The circuit combines the high linearity of a single-bit architecture with the increased stability of a multi-bit converter. Fabricated in a 0.13-/spl mu/m CMOS logic process, it draws 208 /spl mu/A from a 1.25 V nominal supply. Clocked at 1.5 MHz, the input bandwidth is 150 Hz-11 kHz, with an SNR of 84 dB.

Multi-standard low-power DDR I/O circuit design in 7nm CMOS process

This paper presents novel circuit techniques to implement DDR I/O circuit design that can support multiple low-power standards in a state-of-art 7nm CMOS finfet process. Hybrid pull-up driver with a power gating switch is proposed to support a wide range of data rates and output swing levels. The usage of both thin and thick gate oxide devices in the final output stage effectively achieves minimal power consumption while enabling 6.4Gbps/pin data rate. The proposed input receiver directly converts the incoming signals common mode levels to the optimal level of the 1st stage amplifier by a replica feedback loop. Frequency peaking technique is also employed to suppress the inter-symbol interference (ISI) and increase overall bandwidth of the receiver. Simulation results are provided.

Session 11 — Wireline building blocks

This session offers potpourri of advanced subjects for the design of wireline systems. The first paper is a clock multiplier that provides excellent jitter performance (−247db FOM) at 10GHz in a 65nm process using injection locking. The traditional problems of free running frequency drift are addressed with a novel continuous tracking loop.

Amplifiers and filters

This session highlights advances in amplifier and filter design. The subjects of the papers range from the improvements in filter designs for complex active filters to gain enhancement techniques for actively loaded amplifiers. The sessions papers also cover techniques for improving the high frequency distortion performance of amplifiers and a triplet of papers on high performance audio output drivers.

Analog techniques II

The four papers in the session cover progress in the state of the art of analog circuits in data conversion and frequency generation.

Oversampled ADC's

Oversampled ADCs are steadily reaching higher effective bandwidths and resolutions at lower power dissipation levels through the use of clever design techniques. The use of continuous time architecture enhances the system level usability by reducing the need for anti-aliasing filters.