William Pierce Evans

A 12-b 56MS/s pipelined ADC in 65nm CMOS

This paper describes a 1.2V, 12-b pipelined ADC implemented in a 65nm CMOS process. The circuit design techniques used to obtain high gain operational amplifiers in a deep-submicron process are described. A novel top-level simulation methodology is used to quantify the transient errors in each subrange stage, allowing their optimal design. The circuit employs various techniques for power reduction: class A-B op-amps, improved reference design, and frequency-to-current biasing.

A 23fJ/conv-step 12b 290MS/s time interleaved pipelined SAR ADC.

This paper describes the techniques used in the design of a 12-bit 290MS/s two stage time interleaved (TI) SAR ADC that minimizes the sampling skew and gain mismatches between multiple high resolution cores without the need for background digital calibration. A timing scheme which allows sharing of a single reference buffer and optimal distribution of conversion time among MSB and LSB bits is used. Further optimization in power is achieved by use of a process, voltage and temperature (PVT) invariant asynchronous timing loop that avoids pessimistic margins and simplifies design. The ADC is implemented in TSMC 28HPM process and achieves high input frequency figure of merit (FoM) of 23fJ/conv-step. Its high frequency Schreier FoM is 165.3dB, which is the highest reported number at this sampling range. The architecture is extended towards implementation of a 12-bit 460MS/s ADC, where two such instances are interleaved to achieve FoM of 30fJ/conv-step and greater than 70dB SFDR.

Deep submicron effects on data converter building blocks

Physical effects in deep submicron processes can affect reliability, performance, and even functionality in common circuit building blocks used in data converters. NBTI (Negative Bias Temperature Instability), STI (Shallow Trench Isolation) stress, and NWELL proximity effects will be reviewed and examples are given of circuit topologies and layout practices which can minimize the detrimental aspects these effects on commonly used blocks such as comparators, op-amps, and high speed flip-flops.

A low-voltage low-power sigma-delta modulator with improved performance in overload condition

A 4/sup th/-order sigma-delta modulator is presented that offers significantly improved stability and SNR when the input is overloaded, compared to conventional single-bit modulators. The circuit combines the high linearity of a single-bit architecture with the increased stability of a multi-bit converter. Fabricated in a 0.13-/spl mu/m CMOS logic process, it draws 208 /spl mu/A from a 1.25 V nominal supply. Clocked at 1.5 MHz, the input bandwidth is 150 Hz-11 kHz, with an SNR of 84 dB.