Eric Nequist
Cadence Design Systems
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Publication
Featured researches published by Eric Nequist.
custom integrated circuits conference | 1990
Albert H. Chao; Eric Nequist; Thanh Vuong
A practical set of features for meeting the constraints of high performance designs during placement has been developed. The tool observes signal path constraints in units of time, automatically trading off delay between nets on the critical paths. The tool can observe net constraints in units of delay or capacitance. These features are based on a fast and accurate algorithm for net wiring estimation. Using a constraints method enables the true timing problem to be solved better and eliminates design iteration. Additional features specific to ECL design are also available. Results show a 52% reduction in interconnect delay versus an unconstrained placement on the first test case.<<ETX>>
system-level interconnect prediction | 2000
Louis K. Scheffer; Eric Nequist
Archive | 2007
David White; Eric Nequist
Archive | 2003
Steven Lee Pucci; Eric Nequist
Archive | 2011
David Cross; Eric Nequist
Archive | 2003
Jeffrey S. Salowe; Steven Lee Pucci; Eric Nequist
Archive | 2003
Eric Nequist; Jeffrey S. Salowe; Steven Lee Pucci
Archive | 2003
Eric Nequist
international symposium on physical design | 2007
David Cross; Eric Nequist; Louis K. Scheffer
Archive | 2008
David White; Matthew Liberty; Eric Nequist; Michael McSherry