Louis K. Scheffer

Statistical Timing Analysis: From Basic Principles to State of the Art

Static-timing analysis (STA) has been one of the most pervasive and successful analysis engines in the design of digital circuits for the last 20 years. However, in recent years, the increased loss of predictability in semiconductor devices has raised concern over the ability of STA to effectively model statistical variations. This has resulted in extensive research in the so-called statistical STA (SSTA), which marks a significant departure from the traditional STA framework. In this paper, we review the recent developments in SSTA. We first discuss its underlying models and assumptions, then survey the major approaches, and close by discussing its remaining key challenges.

Physical CAD changes to incorporate design for lithography and manufacturability

The next few process generations (65 nm and below) will have serious lithography and manufacturing constraints since the feature size is shrinking much more rapidly than the wavelengths used in manufacturing the chips. This paper starts with a quick tutorial on the Design for Manufacturability problems of these process generations, concentrating primarily on the limitations of optical lithography. The remainder of the talk covers the changes to physical design tools, such as placement and routing, that are needed to cope with these problems.

Timing and crosstalk driven area routing

We present a timing and crosstalk driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a quantitative way. Our graph-based optimizer preroutes wires on the global routing grids incrementally in two stages - net order assignment and space relaxation. The timing delay of each critical path is calculated taking into account interconnect coupling capacitance. The objective is to reduce the delays of critical nets with negative timing slack values, by tuning net ordering and adding extra wire spacing. It shows a remarkable 8.4-25% delay reduction for MCNC benchmarks for wire geometric ratio=2.0, against a 33% delay reduction if interconnect interference disappear.

EDA for IC Implementation, Circuit Design, and Process Technology

Design Flows. Logic Synthesis. Power Analysis and Optimization from Circuit to Register Transfer Levels. Equivalence checking. Digital Layout - Placement. Static Timing Analysis. Structured Digital Design. Routing. Exploring Challenges of Libraries for Electronic Design. Design Closure. Tools for Chip-Package Codesign. Design Databases. FPGA Synthesis and Physical Design. Simulation of Analog and Radio Frequency Circuits and Systems. Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits. Layout Tools for Analog ICs and Mixed-Signal SoCs. Design Rule Checking. Resolution Enhancement Technology and Mask Data Preparation. Design for Manufacturability in the Nanometer Era. Power Supply Network Design and Analysis. Noise Considerations in Digital ICs. Layout Extraction. Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis and Validation. Process Simulation. Device Modeling: From Physics to Electrical Parameter Extraction. High-Accuracy Parasitic Extraction.

Methodologies and tools for pipelined on-chip interconnect

As processes shrink, gate delay improves much faster than the delay in long wires. Therefore, the long wires increasingly determine the maximum clock rate, and hence performance, of more and more chips. One solution to this problem is to pipeline the global interconnect, enabling the whole chip to run at the speed of local operations. While known to work well, this optimization is seldom used because of practical difficulties - it is hard to change the RTL, test vectors become invalid, and its hard to prove correctness of any changes. Here we look at some ways these difficulties could be overcome.

Conventional forces can explain the anomalous acceleration of Pioneer 10

Anderson et al. find the measured trajectories of Pioneer 10 and 11 spacecrafts deviate from the trajectories computed from known forces acting on them. This unmodeled acceleration (and the less well known, but similar, unmodeled torque) can be accounted for by non-isotropic radiation of spacecraft heat. Various forms of non-isotropic radiation were proposed by Katz, Murphy, and Scheffer, but Anderson et al. felt that none of these could explain the observed effect. This paper calculates the known effects in more detail and considers new sources of radiation, all based on spacecraft construction. These effects are then modeled over the duration of the experiment. The model reproduces the acceleration from its appearance at a heliocentric distance of 5 AU to the last measurement at 71 AU to within 10%. However, it predicts a larger decrease in acceleration between intervals I and III of the Pioneer 10 observations than is observed. This is a

Explicit computation of performance as a function of process variation

2\ensuremath{\sigma}

Timing- and crosstalk-driven area routing

discrepancy from the average of the three analyses (SIGMA, CHASMP, and Markwardt). A more complex (but more speculative) model provides a somewhat better fit. Radiation forces can also plausibly explain the previously unmodeled torques, including the spindown of Pioneer 10 that is directly proportional to spacecraft bus heat, and the slow but constant spin-up of Pioneer 11. In any case, by accounting for the bulk of the acceleration, the proposed mechanism makes it much more likely that the entire effect can be explained without the need for new physics.

A roadmap of CAD tool changes for sub-micron interconnect problems

Each manufactured chip is a little bit different, and designers want as many as possible of these chips to work. Process variation is a function of many variables, as the width, thickness, and inter-layer thickness can vary independently for each layer on a chip, as can temperature and voltage. Currently designers cope with this by picking a few subsets of these conditions, called process corners, and analyzing at these conditions. However, its easy to show this approach is both too conservative (the specified conditions will seldom occur) and not conservative enough (it misses errors that can occur due to process variation). We present a unified theory of process variation that includes inter-chip variation, intra-chip deterministic variation (such as caused by proximity effects and metal density), and intra-chip statistical variation. Using this mechanism, we can explicitly compute performance as a function of process variation. This allows us to compute less pessimistic timing numbers and address yield optimization in the design process.

An overview of on-chip interconnect variation

We present a timing- and crosstalk-driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a quantitative way. The new approach fits between global routing and detailed routing along the physical design flow. It is the first to address the timing- and crosstalk-driven area routing problem using crosspoint assignment prior to the detailed routing stage, in contrast to the most previous approaches applied in the post-detailed routing stage. Our new approach enjoys a larger optimization solution space than the previous approaches whose solution space is highly limited by routed geometric constraints. Based on the global routing information, our graph-based optimizer preroutes wires on the global routing grids incrementally. The graph-based optimizer has two stages, net order assignment and space relaxation. A quick capacitance extraction and Elmore delay calculator considering signal switching activities are implemented to find the timing of critical nets and to provide the timing slack database of critical nets. As the graph-based algorithm proceeds, the path delay of critical nets and the timing slack database are updated. During the optimization process, it only optimizes the timing critical paths with negative slack values. The experimental results show a 5%-16% delay reduction for MCNC macrocell benchmark circuits for a 0.25 /spl mu/m process for wire geometric ratio (height/width)=1.0, against a 25% delay reduction if there is infinite space around each metal wire on the same layer.