Eric R. Keiter

Improving performance via mini-applications.

Application performance is determined by a combination of many choices: hardware platform, runtime environment, languages and compilers used, algorithm choice and implementation, and more. In this complicated environment, we find that the use of mini-applications - small self-contained proxies for real applications - is an excellent approach for rapidly exploring the parameter space of all these choices. Furthermore, use of mini-applications enriches the interaction between application, library and computer system developers by providing explicit functioning software and concrete performance results that lead to detailed, focused discussions of design trade-offs, algorithm choices and runtime performance issues. In this paper we discuss a collection of mini-applications and demonstrate how we use them to analyze and improve application performance on new and future computer platforms.

A parallel preconditioning strategy for efficient transistor-level circuit simulation

We describe a parallel computing approach for large-scale SPICE-accurate circuit simulation, which is based on a new strategy for the parallel preconditioned iterative solution of circuit matrices. This strategy consists of several steps, including singleton removal, block triangular form (BTF) reordering, hypergraph partitioning, and a block Jacobi pre-conditioner. Our parallel implementation makes use of a mixed load balance, employing a different parallel partition for the matrix load and solve. Based on message-passing, our circuit simulation code was originally designed for large parallel computers, but for the purposes of this paper we demonstrate that it also gives good parallel speedup in modern multi-core environments. We show that our new parallel solver outperforms a serial direct solver, a parallel direct solver and an alternative iterative solver on a set of circuit test problems.

Redesigning the WARPED simulation kernel for analysis and application development

WARPED is a publicly available time warp simulation kernel. The kernel defines a standard interface to the application developer and is designed to provide a highly configurable environment for the integration of time warp optimizations. It is written in C++, uses the MPI message passing standard, and executes on a variety of parallel and distributed processing platforms. Version 2.0 of WARPED described here is distributed with several applications and the configuration can be set so that a sequential kernel implementation can be instantiated The kernel supports LP clustering, various GVT algorithms, and numerous optimizations to adaptively adjust simulation parameters at runtime.

Parallel Transistor-Level Circuit Simulation

With the advent of multi-core technology, inexpensive large-scale parallel platforms are now widely available. While this presents new opportunities for the EDA community, traditional transistor-level, SPICE-style circuit simulation has unique parallel simulation challenges. Here the Xyce Parallel Circuit Simulator is described, which has been designed from the “from-the-ground-up” to be distributed memory-parallel. Xyce has demonstrated scalable circuit simulation on hundreds of processors, but doing so required a comprehensive parallel strategy. This included the development of new solver technologies, including novel preconditioned iterative solvers, as well as attention to other aspects of the simulation such as parallel file I/O, and efficient load balancing of device evaluations and linear systems. Xyce relies primarily upon a message-passing (MPI-based) implementation, but optimal scalability on multi-core platforms can require a combination of message-passing and threading. To accommodate future parallel platforms, software abstractions allowing adaptation to other parallel paradigms are part of the Xyce design.

Computational Algorithms for Device-Circuit Coupling

Circuit simulation tools (e.g., SPICE) have become invaluable in the development and design of electronic circuits. Similarly, device-scale simulation tools (e.g., DaVinci) are commonly used in the design of individual semiconductor components. Some problems, such as single-event upset (SEU), require the fidelity of a mesh-based device simulator but are only meaningful when dynamically coupled with an external circuit. For such problems a mixed-level simulator is desirable, but the two types of simulation generally have different (sometimes conflicting) numerical requirements. To address these considerations, we have investigated variations of the two-level Newton algorithm, which preserves tight coupling between the circuit and the partial differential equations (PDE) device, while optimizing the numerics for both.

Integrating multiple parallel simulation engines for mixed-technology parallel simulation

The emergence of mixed-signal (analog and digital) integrated circuits motivates the need for CAD tools supporting mixed-signal design and analysis. Furthermore, the presence of a large body of existing models in existing modeling language and the need for modeling mixed-signal (analog and digital) circuits motivates the need for a single unified simulation framework into which different parallel simulation subsystems can be easily connected. In this paper we have review the design of a light-weight simulation backplane for integrating simulators from different domains. Of particular focus for this paper is the integration of a parallel SPICE (analog circuit) simulator called Xyce/sup TM/ with a parallel VHDL (digital circuit) simulator called SAVANT.

Consequences of three-dimensional physical and electromagnetic structures on dust particle trapping in high plasma density material processing discharges

Plasma processing discharges are typically designed with the goal of having uniform reactant fluxes to the substrate and a minimum of dust particle contamination of the wafer. It is not uncommon, however, that reactors have three-dimensional (3D) structures such as antennas (or coils), gas injection nozzles, sub- or super-wafer topography and single-sided pump ports. These structures can contribute to azimuthal asymmetries in reactant fluxes. These structures may also produce dust particle traps. In this paper, a 3D plasma equipment model is applied to investigate the impact of these structures on reactant fluxes and their influence on dust particle trapping in inductively coupled radio frequency discharges under conditions where trapping is not typically obtained. We find that 3D structures, such as injection nozzles, perturb the plasma potential and ion fluxes to distances well beyond their geometrical boundaries. These perturbations are sufficient to create dust particle traps. Electromagnetic asymmetr...

Analytic 1-D

Circuit simulation codes, such as SPICE, are invaluable in the development and design of electronic circuits in radiation environments. These codes are often employed to study the effect of many thousands of devices under transient current conditions. Device-scale simulation codes are commonly used in the design of individual semiconductor components, but computational requirements limit their use to small-scale circuits. Analytic solutions to the ambipolar diffusion equation, an approximation to the carrier transport equations, may be used to characterize the transient currents at nodes within a circuit simulator. We present new analytic transient excess carrier density and photocurrent solutions to the ambipolar diffusion equation for 1-D abrupt-junction pn diodes. These solutions incorporate low-level radiation pulses and take into account a finite device geometry, ohmic fields outside the depleted region, and an arbitrary change in the carrier lifetime due to neutron irradiation or other effects. The solutions are specifically evaluated for the case of an abrupt change in the carrier lifetime during or after, a step, square, or piecewise linear radiation pulse. Noting slow convergence of the Fourier series solutions for some parameters sets, we evaluate portions of the solutions using closed-form formulas, which result in a two order of magnitude increase in computational efficiency.

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The Xyce Parallel Circuit Simulator, which has demonstrated scalable circuit simulation on hundreds of processors, heavily leverages the high-performance scientific libraries provided by Trilinos. With the move towards multi-core CPUs and GPU technology, retaining this scalability on future parallel architectures will be a challenge. This paper will discuss how Trilinos is an enabling technology that will optimize the trade-off between effort and impact for application codes, like Xyce, in their transition to becoming next-generation simulation tools.

Junction Diode Photocurrent Solutions Following Ionizing Radiation and Including Time-Dependent Changes in the Carrier Lifetime From a Nonconcurrent Neutron Pulse

For the purpose of simulating the effects of neutron radiation damage on bipolar circuit performance, a bipolar junction transistor (BJT) compact model incorporating displacement damage effects and rapid annealing has been developed. A physics-based approach is used to model displacement damage effects, and this modeling approach is implemented as an augmentation to the Gummel-Poon BJT model. The model is presented and implemented in the Xyce circuit simulator, and is shown to agree well with experiments and TCAD simulation, and is shown to be superior to a previous compact modeling approach.