Thomas V. Russo

Redesigning the WARPED simulation kernel for analysis and application development

WARPED is a publicly available time warp simulation kernel. The kernel defines a standard interface to the application developer and is designed to provide a highly configurable environment for the integration of time warp optimizations. It is written in C++, uses the MPI message passing standard, and executes on a variety of parallel and distributed processing platforms. Version 2.0 of WARPED described here is distributed with several applications and the configuration can be set so that a sequential kernel implementation can be instantiated The kernel supports LP clustering, various GVT algorithms, and numerous optimizations to adaptively adjust simulation parameters at runtime.

Parallel Transistor-Level Circuit Simulation

With the advent of multi-core technology, inexpensive large-scale parallel platforms are now widely available. While this presents new opportunities for the EDA community, traditional transistor-level, SPICE-style circuit simulation has unique parallel simulation challenges. Here the Xyce Parallel Circuit Simulator is described, which has been designed from the “from-the-ground-up” to be distributed memory-parallel. Xyce has demonstrated scalable circuit simulation on hundreds of processors, but doing so required a comprehensive parallel strategy. This included the development of new solver technologies, including novel preconditioned iterative solvers, as well as attention to other aspects of the simulation such as parallel file I/O, and efficient load balancing of device evaluations and linear systems. Xyce relies primarily upon a message-passing (MPI-based) implementation, but optimal scalability on multi-core platforms can require a combination of message-passing and threading. To accommodate future parallel platforms, software abstractions allowing adaptation to other parallel paradigms are part of the Xyce design.

Computational Algorithms for Device-Circuit Coupling

Circuit simulation tools (e.g., SPICE) have become invaluable in the development and design of electronic circuits. Similarly, device-scale simulation tools (e.g., DaVinci) are commonly used in the design of individual semiconductor components. Some problems, such as single-event upset (SEU), require the fidelity of a mesh-based device simulator but are only meaningful when dynamically coupled with an external circuit. For such problems a mixed-level simulator is desirable, but the two types of simulation generally have different (sometimes conflicting) numerical requirements. To address these considerations, we have investigated variations of the two-level Newton algorithm, which preserves tight coupling between the circuit and the partial differential equations (PDE) device, while optimizing the numerics for both.

Integrating multiple parallel simulation engines for mixed-technology parallel simulation

The emergence of mixed-signal (analog and digital) integrated circuits motivates the need for CAD tools supporting mixed-signal design and analysis. Furthermore, the presence of a large body of existing models in existing modeling language and the need for modeling mixed-signal (analog and digital) circuits motivates the need for a single unified simulation framework into which different parallel simulation subsystems can be easily connected. In this paper we have review the design of a light-weight simulation backplane for integrating simulators from different domains. Of particular focus for this paper is the integration of a parallel SPICE (analog circuit) simulator called Xyce/sup TM/ with a parallel VHDL (digital circuit) simulator called SAVANT.

A Physics-Based Device Model of Transient Neutron Damage in Bipolar Junction Transistors

For the purpose of simulating the effects of neutron radiation damage on bipolar circuit performance, a bipolar junction transistor (BJT) compact model incorporating displacement damage effects and rapid annealing has been developed. A physics-based approach is used to model displacement damage effects, and this modeling approach is implemented as an augmentation to the Gummel-Poon BJT model. The model is presented and implemented in the Xyce circuit simulator, and is shown to agree well with experiments and TCAD simulation, and is shown to be superior to a previous compact modeling approach.

Mixed-signal simulation with the Simbus backplane

In this paper, the Simbus backplane is used in conjunction with SAVANT/TyVIS/WARPED, a parallel VHDL simulator, and Xyce, a parallel SPICE simulation engine, to model and simulate a mixed-signal ASIC-driven charging circuit simulation. In particular, the individual components of an airbag deployment system are described and modeled in the digital and analog domains. A VHDL-based microcontroller interface is designed to control an analog charging circuit based on accelerometer output. The accelerometer and charging circuit are modeled in SPICE and interactions between the two domains are established through the simbus backplane. The results of this study provide evidence of the implementation possibilities available with a mixed-signal system and demonstrate the feasibility of continuing work in multi-domain simulation.

Scheduling optimization on the Simbus backplane

Continuous system models are becoming increasingly more important in the modeling and analysis of complex systems. Unfortunately, the runtime simulation costs required to support continuous modeling can be prohibitive to their use. One technique to decrease simulation runtime costs is mixed-domain simulation where the system is modeled by a mixture of discrete and continuous elements. In those regions where highly detailed information is required, continuous models can be used, and discrete models can be used otherwise. We present a simulation backplane and its scheduling algorithm that can be used to integrate existing discrete and continuous simulators to form a single unified mixed-domain simulation environment.

Building guide : how to build Xyce from source code.

While Xyce uses the Autoconf and Automake system to configure builds, it is often necessary to perform more than the customary %E2%80%9C./configure%E2%80%9D builds many open source users have come to expect. This document describes the steps needed to get Xyce built on a number of common platforms.

Xyce parallel electronic simulator release notes.

The Xyce Parallel Electronic Simulator has been written to support, in a rigorous manner, the simulation needs of the Sandia National Laboratories electrical designers. Specific requirements include, among others, the ability to solve extremely large circuit problems by supporting large-scale parallel computing platforms, improved numerical performance and object-oriented code design and implementation. The Xyce release notes describe: Hardware and software requirements New features and enhancements Any defects fixed since the last release Current known defects and defect workarounds For up-to-date information not available at the time these notes were produced, please visit the Xyce web page at http://www.cs.sandia.gov/xyce.

The use of electric circuit simulation for power grid dynamics

Traditional grid models for large-scale simulations assume linear and quasi-static behavior allowing very simple models of the systems. In this paper, a scalable electric circuit simulation capability is presented that can capture a significantly higher degree of fidelity including transient dynamic behavior of the grid as well as allowing scaling to a regional and national level grid. A test case presented uses simple models, e.g. generators, transformers, transmission lines, and loads, but with the scalability feature it can be extended to include more advanced non-linear detailed models. The use of this scalable electric circuit simulator will provide the ability to conduct large-scale transient stability analysis as well as grid level planning as the grid evolves with greater degrees of penetration of renewables, power electronics, storage, distributed generation, and micro-grids.