Eric Soenen

A Photovoltaic-Driven and Energy-Autonomous CMOS Implantable Sensor

An energy-autonomous and MRI-compatible CMOS implantable sensor is presented that operates by harvesting the energy of the light which penetrates into the tissue. On-chip P+/N-well diodes are used as on-chip photovoltaic cells and in-vivo physiological data is transmitted neuromorphically to the skin surface.

A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS

The growing complexity and small form factors of hand-held consumer electronics are the driving force of more integration. This increases the need for truly embedded DC-DC converters in advanced processes. Traditional analog DC-DC converter architectures do not fit well with low supply voltages. Digital architectures are attractive, but require an analog-to-digital converter (ADC), which can be challenging to design [1–3].

Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS

It is traditionally challenging to implement higher-order PWM closed-loop Class-D audio amplifiers using analog intensive techniques in deep-submicron, low voltage process technologies. This is primarily attributed to reduced power supply, degraded analog transistor characteristics, including short-channel effects, increased flicker noise, random telegraph noise, transistor reliability concerns and passive component performance. In this paper, we introduce a global closed-loop mixed-signal architecture incorporating digital control and integrate a fourth-order amplifier prototype in 55 nm CMOS. A systematic approach to analyze, design and compensate the feedback loop in the digital domain is also presented. The versatility of implementing the loop gain poles and zeros digitally attains high gain throughout the audio band and attenuates residual high frequency ripples around the loop, simultaneously accomplishing improvements in THD+N and PSRR. The overall architecture is inherently amenable to implementation in deep-submicron and is therefore compatible with scaled CMOS. The measured prototype achieves a high 105 dBA SNR, 0.0031% THD+N, 92 dB PSRR and 85% efficiency when supplying 1 W into emulated 8 Ω speaker load. This performance is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies and reports the highest output power (1.5 W) for deep-submicron designs.

Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS

This paper describes design considerations for a digital inductive-switching DC/DC converter suitable for direct battery connection in a deep sub-micron CMOS process. Digital control techniques and robust circuit design methods take advantage of the advanced process technology while avoiding the barriers to direct battery connection and high efficiency, high power density voltage conversion. The approach is verified on a prototype converter, implemented in 40 nm standard bulk CMOS. The design achieves a peak efficiency of 95% for an input range of up to 5.5 V. The transient response is optimized for typical mobile SoC operating conditions and achieves step response times as fast as 35 μs/V under load.

A temperature sensor with a 3 sigma inaccuracy of ±2°C without trimming from −50°C to 150°C in a 16nm FinFET process

Two compact thermal sensors in advanced technologies are compared. One uses a 20nm planar process, while the other uses a 16nm FinFET process. Both produce a digital temperature reading through the ratiometric conversion of a temperature-dependent and a temperature-independent current. The currents are integrated on an on-chip capacitor, which forms part of a single-bit first-order continuous-time JA modulator. As a result, the modulator does not require an extra op-amp and is insensitive to process variations. The 20nm design dissipates 1.1mW, occupies 0.018 mm2 and achieves a total temperature error of +2.5°C from -25°C to 125°C using a one-point trim. For extra accuracy, the 16nm design uses Dynamic Element Matching. Realized completely with FinFET transistors, it dissipates 1.21mW, occupies 0.0126 mm2 and achieves a total error of +2°C from -50°C to 150°C without any trim.

5.9 An 18.75µW dynamic-distributing-bias temperature sensor with 0.87°C(3σ) untrimmed inaccuracy and 0.00946mm 2 area

The temperature sensing of a chip becomes more critical with the increment of the process and circuit complexity. In advanced processes, the heating effect becomes more severe due to the thermal accumulation within the small chip dimension. In order to provide precise and on-chip local thermal sensing, some structures have been demonstrated [1–7]. The paper presents an ultra-low-power, compact and accurate temperature sensor without trimming for the local heat monitors of SOCs. The approach of the dynamic-distributing-bias temperature sensor efficiently reduces the power consumption and chip area simultaneously with accurate digital outputs. The overall area of the circuit is 0.00946mm2, which shows larger than 2× area reduction compared with the prior art [1–3]. The prototype performs state-of-the-art power consumption of 18.75µW and untrimmed relative 3σ inaccuracy [8] achieving 1.64% among the previous compact temperature sensors with process scales smaller than 40nm [3–7].

A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process

A digital LDO regulator provides a wide operating range and high efficiency. Accuracy is improved by using ripple reduction, output level dependent control, and auto-calibration. Fabricated in a 16nm FinFET CMOS process, the regulator accepts an input voltage of 0.65 V to 2.0V and provides a digitally tunable output of 0.4V to 1.3V with a step size of 0.05V. The DC output error is less than ±1% and the minimum drop-out voltage is 0.05 V. Current loads from 0mA to 100mA are supported with a peak current efficiency of 99.85%.

A 105dBA SNR, 0.0031% THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOS

It is traditionally difficult to implement higher order PWM closed loop class-D audio amplifiers using analog techniques. This paper describes a mixed signal approach, implementing a 4th order amplifier in 55nm CMOS with minimal demands on a front-end ADC. An approach to design the feedback loop in the digital domain with high gain throughout the audio band (100dB at DC) to improve linearity and PSRR is also outlined. The prototype achieves 105dBA SNR, 0.0031% THD+N, 92dB PSRR and 85% efficiency when supplying 1W into emulated 8Q microphone load. This performance represents an improvement over reported designs in advanced nodes and is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies.

A wide-range DC/DC converter with 2 nd order digital compensation and direct battery connection in 40nm CMOS

This paper presents a digital DC-DC converter with 2nd order compensation and direct battery connect capability in 40nm CMOS. A combination of circuit and process technology is used to achieve an input range up to 5.5V with peak efficiencies of 95%. It also outlines an approach to optimize a control loop based on a sigma-delta ADC and higher order digital filter, which is demonstrated on a prototype achieving step response times under load below 38µs/V.