Martin Kinyua

A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS

The growing complexity and small form factors of hand-held consumer electronics are the driving force of more integration. This increases the need for truly embedded DC-DC converters in advanced processes. Traditional analog DC-DC converter architectures do not fit well with low supply voltages. Digital architectures are attractive, but require an analog-to-digital converter (ADC), which can be challenging to design [1–3].

Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS

It is traditionally challenging to implement higher-order PWM closed-loop Class-D audio amplifiers using analog intensive techniques in deep-submicron, low voltage process technologies. This is primarily attributed to reduced power supply, degraded analog transistor characteristics, including short-channel effects, increased flicker noise, random telegraph noise, transistor reliability concerns and passive component performance. In this paper, we introduce a global closed-loop mixed-signal architecture incorporating digital control and integrate a fourth-order amplifier prototype in 55 nm CMOS. A systematic approach to analyze, design and compensate the feedback loop in the digital domain is also presented. The versatility of implementing the loop gain poles and zeros digitally attains high gain throughout the audio band and attenuates residual high frequency ripples around the loop, simultaneously accomplishing improvements in THD+N and PSRR. The overall architecture is inherently amenable to implementation in deep-submicron and is therefore compatible with scaled CMOS. The measured prototype achieves a high 105 dBA SNR, 0.0031% THD+N, 92 dB PSRR and 85% efficiency when supplying 1 W into emulated 8 Ω speaker load. This performance is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies and reports the highest output power (1.5 W) for deep-submicron designs.

Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS

This paper describes design considerations for a digital inductive-switching DC/DC converter suitable for direct battery connection in a deep sub-micron CMOS process. Digital control techniques and robust circuit design methods take advantage of the advanced process technology while avoiding the barriers to direct battery connection and high efficiency, high power density voltage conversion. The approach is verified on a prototype converter, implemented in 40 nm standard bulk CMOS. The design achieves a peak efficiency of 95% for an input range of up to 5.5 V. The transient response is optimized for typical mobile SoC operating conditions and achieves step response times as fast as 35 μs/V under load.

A 105dBA SNR, 0.0031% THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOS

It is traditionally difficult to implement higher order PWM closed loop class-D audio amplifiers using analog techniques. This paper describes a mixed signal approach, implementing a 4th order amplifier in 55nm CMOS with minimal demands on a front-end ADC. An approach to design the feedback loop in the digital domain with high gain throughout the audio band (100dB at DC) to improve linearity and PSRR is also outlined. The prototype achieves 105dBA SNR, 0.0031% THD+N, 92dB PSRR and 85% efficiency when supplying 1W into emulated 8Q microphone load. This performance represents an improvement over reported designs in advanced nodes and is competitive with conventional designs using large feature size precision CMOS or specialized BCD technologies.