Eric Tell

Bridging dream and reality: Programmable baseband processors for software-defined radio

A programmable radio baseband signal processor is one of the essential enablers of software- defined radio. As wireless standards evolve, the processing power needed for baseband processing increases dramatically and the underlying hardware needs to cope with various standards or even simultaneously maintaining several radio links. Meanwhile, the maximum power consumption allowed by mobile terminals is still strictly limited. These challenges require both system and architecture level innovations. This article introduces a design methodology for radio baseband processors discussing the challenges and solutions of radio baseband signal processing. The LeoCore architecture is presented here as an example of a baseband processor design aimed at reducing power and silicon cost while maintaining sufficient flexibility.

An 11mm 2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOS

In this paper a fully- programmable baseband processor enabling standards such as mobile WiMAX and DVB-T/H is presented. This processor outperforms comparable fixed-function circuits for DVB-T/H.

A converged hardware solution for FFT, DCT and Walsh transform

In this paper, we are interested in developing a programmable baseband processor for multiple radio standards, including the wireless LAN standards 802.11a and 802.11b. 802.11a is based on OFDM and uses a 64-point FFT. Demodulation of the complementary code keying (CCK) used in 802.11b includes the computation of a modified Walsh transform. Similarities have been found between the radix-4 FFT and the fast Walsh transform (FWT) and this has enabled the design of a converged FFT and FWT processor. With small modifications this processor can also be used for calculating the discrete cosine transform (DCT). A converged FFT/FWT/DCT processor was designed and synthesized in a 0.13/spl mu/m process. Results indicate that the hardware can run at 385 MHz, which means a 64-point FFT/DCT is calculated in 140 ns and a FWT for 802.11b 11Mb/s CCK in 47 ns. The area including memory is 0.40 mm/sup 2/.

A low area and low power programmable baseband processor architecture

Fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and number flexible accelerators, connected via a configurable network. Design choices are motivated by the inherent properties of the baseband algorithms used in different types of radio systems. A large degree of hardware reuse between algorithms and standards, careful selection of accelerators, and low memory cost allows very area and power efficient implementation of multi-standard radio baseband processors. A demonstrator chip for 802.11 a/b/g physical layer baseband processing was manufactured in 0.18 /spl mu/m CMOS. The silicon area is 2.9 mm/sup 2/, including all memories.

System architecture for 3GPP LTE modem using a programmable baseband processor

3G evolution towards HSPA (High Speed Packet Access) and LTE (Long-Term Evolution) is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier demapping. The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ. This brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.

A programmable DSP core for baseband processing

A programmable baseband processor architecture is presented. The architecture is based on a specialized DSP processor core and a number accelerators connected via a configurable network. The focus of this paper is the DSP core itself. A novel type of instructions operating on vectors of complex data is used. Implementation of a demonstrator chip and firmware for wireless LAN applications has proven the instruction set to be very efficient, resulting in low program memory cost and moderate clock frequency requirements. The architecture also minimizes data memory size and accesses, which together with a high degree of hardware reuse results in very low silicon cost for multi-standard baseband processors.

Design methodology for memory-efficient multi-standard baseband processors

Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband processors. The methodology yields baseband processor micro-architectures, which eliminate excessive data moves between memories while still allowing true flexibility by utilizing SIMD clusters connected to memory banks via an internal network. The methodology has successfully been used to create a multi-standard baseband processor for OFDM-based wireless standards. This paper discusses the IEEE 802.16e (WiMAX), DVB-H (digital video broadcast - handheld) and DAB (digital audio broadcast) standards. The architecture is truly scalable to accommodate future OFDM systems. Scheduling and resource allocation show that with the proposed memory structure and architecture, the processor can manage the baseband functions of the described standards operating at 80 MHz and using only 28k words of memory

Simultaneous multi-standard support in programmable baseband processors

Programmability is increasingly important in future multi-standard radio systems. In this paper we present enhanced baseband processor architecture capable of efficiently supporting simultaneous multi-standard operation. Our DSP processor is based on the SIMT (single instruction stream multiple tasks) architecture which allows concurrent vector tasks to be executed on the processor controlled by only a single narrow instruction stream. By profiling and mapping GSM and WLAN (IEEE 802.11g) to the architecture we show that simultaneous support for the above mentioned standards can be accomplished with 245 MHz clock frequency and 1359 words of complex data memory on the given architecture

System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor

3G evolution towards HSPA (High Speed Packet Access) and LTE (Long-Term Evolution) is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier demapping. The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ. This brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.

MIPS cost estimation for OFDM-VBLAST systems

The focus of this paper is to investigate the feasibility of using programmable DSP processors for MIMO based radio systems. Several detection algorithms were evaluated and MIPS costs for low complexity detection and channel estimation algorithms for OFDM-VBLAST MIMO systems where calculated. Based on the MIPS cost estimation a feasible hardware architecture was derived. The result shows the feasibility of implementing MIMO radio systems in a programmable architecture