Rizwan Asghar

Dual standard re-configurable hardware interleaver for turbo decoding

A very low cost re-configurable hardware interleaver for two standards, 3GPP-WCMDA and 3GPP Long Term Evolution (3GPP-LTE) is presented. The interleaver is a key component of radio communication systems. Using conventional design methods, it consumes a large part of silicon area in the design of turbo encoder and decoder. The presented hardware interleaver address generation architecture, utilizes the algorithmic level hardware simplifications to achieve very low cost solution. After doing the hardware optimizations the proposed architecture consumes only 3.1 k gates with a 256 times 8 bit memory for the fully re-configurable dual standard interleaver address generator. The interleaved address is computed every clock cycle except the case of pruning (if block size is less than the row-column matrix) in 3GPP-WCDMA. In this case one additional clock cycle is consumed for valid address generation.

Implementation of a high-speed parallel Turbo decoder for 3GPP LTE terminals

This paper presents a parameterized parallel Turbo decoder for 3GPP LTE terminals. To support the high peak data-rate defined in the forthcoming 3GPP LTE standard, Turbo decoder with a throughout beyond 150Mbit/s is needed as a key component of the radio baseband chip. By exploiting the tradeoff of precision, speed and area consumption, a Turbo decoder with eight parallel SISO units is implemented to meet the throughput requirement. The turbo decoder is synthesized, placed and routed using 65nm CMOS technology. It achieves a throughput of 152Mbit/s and occupies an area of 0.7mm2 with estimated power consumption being 650mW1.

VLSI implementation of a fixed-complexity soft-output MIMO detector for high-speed wireless

This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO) detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

Towards radix-4, parallel interleaver design to support high-throughput turbo decoding for re-configurability

Parallel, radix-4 turbo decoding is used to enhance the throughput and at the same time reduce the overall memory cost. The bottleneck is the higher complexity associated with radix-4 parallel interleaver implementation. This paper addresses the implementation issues of radix-4, parallel interleaver and also proposes necessary modifications in the interleaver algorithms for parallel address generation. It presents a re-configurable architecture which enables the use of same turbo decoding core to be used for multiple standards. The proposed interleaver architecture is capable of handling the memory conflicts on-the-fly. It consumes 12.5K gates and can run at a frequency of 285MHz, thus supporting a throughput of 173.3Mpbs, which can cover most of the emerging communication standards.

Low complexity hardware interleaver for MIMO-OFDM based wireless LAN

A low complexity hardware interleaver architecture is presented for MIMO-OFDM based Wireless LAN e.g. 802.11n. Novelty of the presented architecture is twofold; 1) Flexibility to choose interleaver implementation with different modulation scheme and different size for different spatial streams in a multi antenna system, 2) Complexity to compute on the fly interleaver address is reduce by using recursion and is supported by mathematical formulation. The proposed interleaver architecture is implemented on 65nm CMOS process and it consumes 0.035 mm2 area. The proposed architecture supports high speed communication with maximum throughput of 900 Mbps at a clock rate of 225 MHz.

Very Low Cost Configurable Hardware Interleaver for 3G Turbo Decoding

A very low cost hardware interleaver for 3rd Generation Partnership Project (3GPP) turbo coding algorithm is presented. The interleaver is a key component of turbo codes and it is used to minimize the effect of burst errors in the transmission. Using conventional design methods, it consumes a large part of silicon area in the design of turbo encoder and decoder. The presented hardware interleaver architecture utilizes the algorithmic level hardware simplifications as well as the iterative modulo computation to achieve very low cost solution. After doing the hardware multiplexing and optimization the proposed architecture consumes only 1.5 k gates (without pre-computation) and 2.2 k gates (with pre- computation). In both cases the interleaved address is computed every clock cycle except the case of pruning, in which one additional clock cycle is consumed.

Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution

HSPA evolution has raised the throughput requirements for WCDMA based systems where turbo code has been adapted to perform the error correction. Many parallel turbo decoding architectures have rece ...

VLSI implementation of A multi-standard MIMO symbol detector for 3GPP LTE and WiMAX

In this paper, a low-complexity symbol detector is presented targeting the emerging 3GPP LTE and WiMAX standards. The detector is the VLSI implementation of a novel MIMO detection algorithm recently proposed. Compared to the design in the reference, the detector performs better while consumes less silicon area. Including a microcode controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover different standards and transmission schemes while maintaining the power and area efficiency. Implemented using 65 nm CMOS process, the detector can support real-time detection of 20 MHz bandwidth 3GPP LTE or 10 MHz WiMAX downlink physical channel.

Multimode flex-interleaver core for baseband processor platform

This paper presents a flexible interleaver architecture supporting multiple standards like WLAN, WiMAX, HSPA+, 3GPP-LTE, and DVB. Algorithmic level optimizations like 2D transformation and realization of recursive computation are applied, which appear to be the key to reach to an efficient hardware multiplexing among different interleaver implementations. The presented hardware enables the mapping of vital types of interleavers including multiple block interleavers and convolutional interleaver onto a single architecture. By exploiting the hardware reuse methodology the silicon cost is reduced, and it consumes 0.126mm2area in total in 65 nm CMOS process for a fully reconfigurable architecture. It can operate at a frequency of 166 MHz, providing a maximum throughput up to 664 Mbps for a multistream system and 166 Mbps for single stream communication systems, respectively. One of the vital requirements for multimode operation is the fast switching between different standards, which is supported by this hardware with minimal cycle cost overheads. Maximum flexibility and fast switchability among multiple standards during run time makes the proposed architecture a right choice for the radio baseband processing platform.

System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor

3G evolution towards HSPA (High Speed Packet Access) and LTE (Long-Term Evolution) is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier demapping. The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ. This brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.