Eric Y. Chou

VLSI design of optimization and image processing cellular neural networks

Detailed design of a current-mode cellular neural network for optimization and image processing is presented. The hardware annealing function is also embedded in the network. It is a paralleled version of fast mean-field annealing in analog networks, and is highly efficient in finding globally optimal solutions for cellular neural networks. The network was designed to perform programmable functions for fine-grained processing with annealing control to enhance the output quality. A 5/spl times/5 prototype chip was fabricated in a 2.0 /spl mu/m CMOS technology. Since the MOSIS scalable design rules are used, it is also suitable for submicron technologies. For high circuit reliability and compactness purpose, a unit current of 6.0 /spl mu/A is used. The cell density is 505 cell/cm/sup 2/ and the cell time constant is chosen to be 0.3 /spl mu/s. From this prototype, a scalable VLSI core of around 50/spl times/50 neural processors can be integrated on a 1-cm/sup 2/ silicon area in a 0.8 /spl mu/m technology. Experimental results of building blocks and the prototype chip are also presented.

Nanometer mixed-signal system-on-a-chip design

A mixed-signal system-on-a-chip (SoC) design methodology and the supporting CAD tools are presented. A known tools set is identified for illustration purposes and some alternative tools can equally accomplish the task.

System-on-a-chip design for modern communications

In this article, the trends and opportunities in SoC IC design for the networking communication industry is presented. These trends will significantly affect innovation and practice of the microelectronics business in the future. Microchip development and deployment will not be treated as pure components business. In fact, it will become a solution-oriented business that requires knowledge of electronics, software, systems, and soft skills such as business, marketing, psychology for human factors, etc.

A hardware annealing method for optimal solutions on cellular neural networks

An engineering annealing method, called hardware annealing, for optimal solutions on cellular neural networks is presented. Cellular neural networks have great potential in solving many important scientific problems in signal processing and optimization by use of pre-determined templates. Hardware annealing, which is a parallel version of effective mean-field annealing in analog networks, is a highly efficient method to find optimal solutions on cellular neural networks. It does not require any iterative stochastic procedure and henceforth can be very fast. The landscape of the network energy function is first adapted so that the whole annealing process does not get stuck at a local minimum at the beginning of searching for optimal solutions by adjusting each neuron to a low voltage gain. Then, the hardware annealing searches for the globally minimum energy state by continuously increasing the gain of neurons. The globally optimal equilibrium state is reached when each neuron is at its maximum voltage gain. The robustness of this proposed hardware annealing method for global optimization is assessed by analysis of the eigenvalues in a corresponding dynamical system model.

A state-constrained model for cellular nonlinear network optimization

A G/sub m/C-style state constrained neuron (SCN) model for the design of processors in analog recurrent neural networks such as Hopfield neural networks, cellular nonlinear networks for combinatorial optimization is described. The unconstrained neurons which have the free state variable, could be stable at any arbitrary point in the solution space or trapped by un-intentional effects. These may introduce errors. For the unconstrained network, the solution could be different from the expected one due to the discrepancy in the energy function of the network and the objective function to be optimized. In addition, if the state variable is limited by some neighboring saturated transistors, un-desirable results may be obtained. The G/sub m/C-style SCN model can ensure the convergence of the network and avoid discrepancy between the energy function of the network and the objective function. The state resistor is also eliminated in the G/sub m/C model so that high cell-density can be achieved. Simulation results show that the proposed model is effective in significantly reducing optimization error.

A hippocampal model implementation using VLSI table-look-up and model-based approaches

The hippocampus region of the brain system performs cognitive functions of learning and memory. VLSI design of a hippocampal model has been proposed and two mixed analog-digital chips which use analog circuits for parallel computing and digital circuits for interconnection were designed. The design with one extensive hippocampal neuron has been sent for fabrication. One of the objectives of this research effort is to incorporate adequate biological constraints into the microelectronic chips and systems.

A compact neural network for partial-response maximum-likelihood detectors: algorithmic study

A compact neural network algorithm for partial-response maximum-likelihood (PRML) sequence detection is presented. Compact neural networks are a class of locally connected neural networks suitable for very large scale integration (VLSI) implementation. The hardware complexity for VLSI implementation of the proposed algorithm grows linearly with the level of the deliberately designed symbol interference effects of the partial-response (PR) signalling scheme. Large dedicated memory for storage of likelihood matrices in digital Viterbi-algorithm-based detectors is not needed for the proposed detector. Detailed analysis on network stability for network topology and time constant of an analog neuron is described. This detector algorithm has competitive bit-error rate performance when compared with the digital Viterbi algorithm under the noise condition for many real-world applications. The proposed algorithm is suitable for analog VLSI implementation because of its low time complexity and linear area complexity for the detection of PRML signalling schemes.

Behavioral simulation of densely-connected analog cellular array processors for high-performance computing

The analog cellular neural network (CNN) model is a powerful parallel processing paradigm in solving many scientific and engineering problems. The network consists of densely-connected analog computing cells. Various applications can be accomplished by changing the local interconnection strengths, which are also called coefficient templates. The behavioral simulator could help designers not only gain insight on the system operations, but also optimize the hardware-software co-design characteristics. An unique feature of this simulator is the hardware annealing capability which provides an efficient method of finding globally optimal solutions. This paper first gives an overview of the cellular network paradigm, and then discusses the nonlinear integration techniques and related partition issues, previous work on the simulator and our own simulation environment. Selective simulation results are also presented at the end.

A compact VLSI design for recursive neural networks with hardware annealing capability

In this paper, we present a compact CMOS VLSI design for recursive neural networks with the capability of hardware annealing. Locally-connected recursive neural networks are a class of analog nonlinear networks which can solve many important optimization, and signal processing problems and is suitable for VLSI implementation because of its low demand on inter-cell connections. Hardware annealing, which is a paralleled version of effective mean-field annealing in analog networks, is a highly-efficient method to find global optimal solutions of recursive neural networks. A two-neuron prototype chip to demonstrate the functionality of hardware annealing is designed, analyzed and implemented in 2.0 /spl mu/m CMOS technology using mixed-signal design methodology through MOSIS. For circuit reliability and compactness, a unit current of 6 /spl mu/A is used. The cell density is 505 cells/cm/sup 2/ and the cell time constant time is designed to be 0.3 /spl mu/s. Laboratory experimental results to show the behavior of this two neuron chip was produced with annealing control signals from a function generator.

A neural network communication equalizer with optimized solution capability

Artificial neural network approaches in communication have been motivated by the adaptive learning capability and the collective computational properties to process real world signals. In this paper, a one-dimensional compact neural network receiver as a paralleled computational framework of the maximum likelihood sequence estimation (MLSE) is presented. Optimum solution can be obtained by applying the hardware annealing which is a deterministic method for searching a globally minimum energy state in a short period of time.