Robert Chen-Hao Chang

Iterative

Implementation of an iterative QR decomposition (QRD) (IQRD) architecture based on the modified Gram-Schmidt (MGS) algorithm is proposed in this paper. A QRD is extensively adopted by the detection of multiple-input-multiple-output systems. In order to achieve computational efficiency with robust numerical stability, a triangular systolic array (TSA) for QRD of large-size matrices is presented. In addition, the TSA architecture can be modified into an iterative architecture that is called IQRD for reducing hardware cost. The IQRD hardware is constructed by the diagonal and the triangular process with fewer gate counts and lower power consumption than TSAQRD. For a 4 t 4 matrix, the hardware area of the proposed IQRD can reduce about 41% of the gate counts in TSAQRD. For a generic square matrix of order m IQRD, the latency required is 2m - 1 time units, which is based on the MGS algorithm. Thus, the total clock latency is only 10 m - 5 cycles.

QR

In this paper, a new low-voltage charge pump circuit is presented. Its simple and symmetric structure can provide more stable operation. The proposed charge pump circuit is composed of a pair of symmetric pump circuits and a wide-swing current mirror circuit. To ensure more accurate charge pumping operation, a weak pull-up circuit is inserted in the symmetric pump circuit. The new charge pump circuit has wide output range and no jump phenomenon. It has been designed by using the MOSIS 0.35 /spl mu/m double-poly triple-metal CMOS technology and simulated by HSPICE. The power consumption of the proposed charge pump circuit is 0.03 mW at a supply voltage of 1.5 V. The circuit can be widely used in either single-ended or fully differential phase-locked loop structures.

Decomposition Architecture Using the Modified Gram–Schmidt Algorithm for MIMO Systems

In this brief, a high-speed space-division multiplexing (SDM) multiple-input-multiple output (MIMO) decoder using efficient candidate searching is proposed by exploiting the characteristics of QR decomposition and sphere decoder for high throughput rate and low hardware-complexity. A process of efficient candidate searching by shifting the center of constellation with scalable radius reduces the processing time and improves the operational frequency. The proposed architecture can operate at a 166-MHz clock frequency, and the core area is smaller than results from using the K-best SD algorithm since large memory is not required to store extreme candidate paths. In our implementation, the core area is 0.675 mm using TSMC 90-nm technology. The average throughput of the proposed SDM-MIMO decoder is 95 Mbps with 64-QAM modulation at 30-dB signal-to-noise ratio.

A new low-voltage charge pump circuit for PLL

This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-mum 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 mum x 381 mum.

A High-Speed SDM-MIMO Decoder Using Efficient Candidate Searching for Wireless Communication

Although the maximum transmission speed in IEEE 802.11a WLAN is 54 Mbps, the real throughput is actually limited to 20~30 Mbps. Except for the main effect from multi-path, we should also consider some non-ideal effects from imperfect hardware design, such as the IQ imbalance from direct conversion in RF front-end. IQ imbalance is not apparent in lower-order QAM modulation. However, in higher-order QAM modulation, it will become serious interference. In this paper, an IQ imbalance compensation circuit in IEEE802.11a baseband receiver is proposed. A low complexity time-domain compensation algorithm is used to replace the traditional high-order equalizer. MATLAB is used to simulate the whole transceiver including the channel model. After system verification, we use Verilog to implement the IQ imbalance compensation circuit with UMC 0.18 mum CMOS 1p6m technology. Post-layout simulation results show that this scheme contributes to a very robust and easily implemented OFDM WLAN receiver

A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

This work presents a novel synchronization architecture for a 2times2 MIMO OFDM WLAN system. A new CORDIC-based sinusoidal iterative oscillator architecture is also implemented to recover the carrier frequency. The proposed design mainly enhances the traditional digital oscillator, which is a CORDIC-based architecture, and which is adopted at each accumulated phase. Compared to the iterative CORDIC computation, the proposed CORDIC-based sinusoidal iterative oscillator architecture operates the CORDIC only once. Moreover, the timing controller negotiates these two antenna input signals, and gates the useless signal to lower the power consumption. The proposed architecture with high precision is simulated and emulated by 0.18 mum 1P6M CMOS technology and FPGA respectively

Implementation of digital IQ imbalance compensation in OFDM WLAN receivers

A novel pulse frequency modulation step-up dc-dc converter with maximum power conversion of 91.91% and steady-state accuracy of 0.33% is presented in this letter. The high efficiency and exact output are achieved by a dynamic stored energy technique that enhances utility rate of energy with less power consumption. This technique uses a dynamic sensing current controller and a load current detector that accurately generates different energy according to various load conditions. The boost converter has been designed and fabricated with a standard TSMC 3.3/5 V 0.35- mum 2P4M CMOS technology. Experimental results show that the output up-ripple voltage variation was 2.5 mV (6.1-8.6 mV), whereas its fixed energy counterpart was 39.4 mV (8.6-48 mV). The proposed boost converter has 16% higher power conversion efficiency than the conventional fixed energy technique at 1 mA load current.

Implementation of synchronization for 2x2 MIMO WLAN system

Detailed design of a current-mode cellular neural network for optimization and image processing is presented. The hardware annealing function is also embedded in the network. It is a paralleled version of fast mean-field annealing in analog networks, and is highly efficient in finding globally optimal solutions for cellular neural networks. The network was designed to perform programmable functions for fine-grained processing with annealing control to enhance the output quality. A 5/spl times/5 prototype chip was fabricated in a 2.0 /spl mu/m CMOS technology. Since the MOSIS scalable design rules are used, it is also suitable for submicron technologies. For high circuit reliability and compactness purpose, a unit current of 6.0 /spl mu/A is used. The cell density is 505 cell/cm/sup 2/ and the cell time constant is chosen to be 0.3 /spl mu/s. From this prototype, a scalable VLSI core of around 50/spl times/50 neural processors can be integrated on a 1-cm/sup 2/ silicon area in a 0.8 /spl mu/m technology. Experimental results of building blocks and the prototype chip are also presented.

An Exact Current-Mode PFM Boost Converter With Dynamic Stored Energy Technique

Implementation of an iterative QR decomposition (QRD) (IQRD) architecture based on the modified Gram-Schmidt (MGS) algorithm is proposed in this paper. A QRD is extensively adopted by the detection of multiple-input-multiple-output systems. In order to achieve computational efficiency with robust numerical stability, a triangular systolic array (TSA) for QRD of large-size matrices is presented. In addition, the TSA architecture can be modified into an iterative architecture that is called IQRD for reducing hardware cost. The IQRD hardware is constructed by the diagonal and the triangular process with fewer gate counts and lower power consumption than TSAQRD. For a 4 × 4 matrix, the hardware area of the proposed IQRD can reduce about 41% of the gate counts in TSAQRD. For a generic square matrix of order m IQRD, the latency required is 2m - 1 time units, which is based on the MGS algorithm. Thus, the total clock latency is only 10 m - 5 cycles.

VLSI design of optimization and image processing cellular neural networks

An improved implementation of QR decomposition for MIMO-OFDM detection based on the Givens rotation method is presented in this paper. The hardware of QR decomposition is constructed by coordinate rotation digital computer (CORDIC) operating with fewer gate counts and lower power consumption than triangular systolic array structures. In wireless communication systems, the accuracy for transmitting signals is essential. Thus, a better data detection algorithm and precise channel estimation method plays an important role here. The channel estimation implemented with QR decomposition is to reduce hardware complexity of MIMO-OFDM detection. The results of implementation reveal that the proposed QR decomposition architecture has shorter clock latency than folding structure and smaller hardware area than Gram-Schmidt.