Ericson Chua

Mixed bio-signal lossless data compressor for portable brain-heart monitoring systems

This paper presents a highly integrated VLSI implementation of a mixed bio-signal lossless data compressor capable of handling multichannel electroencephalogram (EEG), electrocardiogram (ECG) and diffuse optical tomography (DOT) bio-signal data for reduced storage and communication bandwidth requirements in portable, wireless brain-heart monitoring systems used in hospital or home care settings. The compressor integrated in a multiprocessor brain-heart monitoring IC comprises 15 k gates and 12 kbits of RAM, occupying a total area of 58 k μm2 in 65 nm CMOS technology. Results demonstrate an average compression ratio (CR) of 2.05, and a simulated power consumption of 170 μW at an operating condition of 24 MHz clock and 1.0 V core voltage. Nominal power savings of 43% and 47% at the transmitter can be achieved when employing Bluetooth and Zigbee transceivers, respectively.

A low power biomedical signal processing system-on-chip design for portable brain-heart monitoring systems

In this paper, an overview of a brain-heart monitoring system is first given. The latest development in miniature brain-heart monitoring system for emerging health applications is highlighted. Finally, the development of a low power biomedical signal processing and image reconstruction SoC design is presented. The significance of this SoC is to enable practical developments of portable real-time brain-heart monitoring systems. The proposed architecture comprises a novel functional near-infrared (fNIR) diffuse optical tomography system for brain imaging, an independent component analysis (ICA) processor for electroencephalogram (EEG) signal analysis, and a heart rate variability (HRV) analysis processor for electrocardiogram (ECG) signal analysis. Biomedical signals acquired from front-end sensor modules are processed in real-time or bypassed according to user settings. The processed data or biomedical signals is then losslessly compressed and sent to a remote science station for further analysis and 3D visualization. The final SoC is fabricated in UMC 90nm CMOS technology.

A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.

RF-powered Li-ion battery charger for biomedical applications

An integrated RF-powered Li-ion battery charger solution has been developed for biomedical applications. RF energy received through an antenna is rectified, regulated, and passed on to a battery charger circuit that charges a Li-ion battery efficiently and accurately. The charger system has been implemented using UMC 90nm BiCMOS process library. Experimental results show that a battery model with internal resistance of 300mΩ and internal capacitance of 10mF can be charged to its full capacity at 3.5V in 0.2ms by a 2mW 10MHz RF power source referred from the antenna. The implemented charger circuit consumes only 240 uW.

A low power independent component analysis processor in 90nm CMOS technology for portable EEG signal processing systems

This paper presents a low-power VLSI implementation of a 4-channel independent component analysis (ICA) processor for portable EEG signal processing applications. The low-power scheme employed for this ICA chip is based on power gating and clock gating by utilizing Cadence common power flow (CPF) low-power methodology and also according to the characteristics of ICA training behavior using different training window sizes. The proposed low power ICA processor can separate EEG and mixed EEG-like super-Gaussian signals in real time. The chip can be operated at up to 60MHz working frequency and a maximum sampling rate of 9.394 KHz for EEG signals. The power consumption of this chip is 0.690 mW during training under the condition of 0.9V supply voltage and 10 MHz operating frequency using UMC 90nm High-Vt CMOS technology. The total chip area is 1230 × 1230 µm2.

VLSI implementation of a mixed bio-signal lossless data compressor for portable brain-heart monitoring systems

This paper presents a highly integrated VLSI implementation of a mixed bio-signal lossless data compressor capable of handling multichannel electroencephalogram (EEG), electrocardiogram (ECG) and diffuse optical tomography (DOT) bio-signal data for reduced storage and communication bandwidth requirements in portable, wireless brain-heart monitoring systems for use in the hospital or home care setting.

Implementation of a hardware-efficient EEG processor for brain monitoring systems

This paper presents a complexity-efficient architecture for an EEG signal separation processor incorporating ICA with lossless data compression. An average correlation result of 0.9044 is achieved while transmitted EEG data bandwidth and power consumption are reduced by 41.6%. The chip area, operating frequency, and estimated power consumption of the proposed EEG architecture in UMC 90nm SP-HVT CMOS technology are 1,133 by 1,133 um2, up to 32MHz, and approximately 0.70mW at 0.9V supply voltage and 5 MHz operating frequency, respectively.

A highly-integrated biomedical multiprocessor system for portable brain-heart monitoring

In this paper, a highly-integrated multiprocessor chip design enabling the real-time processing of biomedical signals in portable brain-heart monitoring systems is presented. The architecture comprises a novel diffuse optical tomography (DOT) processor for taking brain imaging, an independent component analysis (ICA) processor for removing artifacts of brain electroencephalogram (EEG) signals, and a heart rate variability (HRV) analysis processor for monitoring heart electrocardiogram (ECG) signals. The multiprocessor chip implemented in 65nm CMOS technology comprises 368k gates and occupies a core area of 462k µm2. Simulated power consumption using a full operation test case reports 3.6mW under the condition of 1.0V core supply voltage and 24MHz clock operating frequency.

A Hardware Design for Portable Continuous Wave Diffuse Optical Tomography

In recent years, the rapid development of diffuse optical tomography (DOT) technology has made possible many successful applications in the field of biomedicine, such as breast cancer detection and observation of oxygenated hemoglobin distribution in the brain. In this work, we build an inexpensive and portable real-time continuous wave near-infrared (CW-NIR) DOT system hardware suitable for use in system on a chip (SOC) applications. With greatly reduced system volume, the system can pave the way for practical develop- ments in the clinical setting. The proposed system processes digitized biomedical signals acquired from a front-end sensor circuit, and can operate in either continuous or discontinuous mode according to user settings. Finally, we demonstrate the improvements in image reconstruction associated with the two-dimensional (2D) post-processing technique employed in the proposed system.

Portable Brain-Heart Monitoring System

A portable brain-heart monitoring system is proposed to integrate and miniaturize those heavy equipments in the hospitals. The system comprises a 4-channel independent component analysis (ICA) engine for artifact removal from EEG, a heart-rate variability (HRV) analysis engine for on-line HRV analysis and a diffuse optical tomography (DOT) engine for reconstruction of the absorption coefficient image of the brain tissue. A lossless compression module achieves 2.5 compression ratio is also employed to reduce the power consumption of the wireless transmission. EEG, EKG and near-infrared signals acquired from the analog front-end IC are processed in real-time or bypassed according to user configurations. Processed data and raw data are compressed and sent to a remote science station by a commercial Bluetooth module for further analysis and 3-D visualization and remote diagnosis. The ICA and HRV engine are verified by real EEG and EKG signals while the DOT engine is verified by an experimental model. The system is implemented using UMC 65nm CMOS technology, and the core size is 680x680 um2, and the estimated power consumption of the chip working at 24 MHz under full mode is 3.6 mW.