Wai-Chi Fang

Mixed bio-signal lossless data compressor for portable brain-heart monitoring systems

This paper presents a highly integrated VLSI implementation of a mixed bio-signal lossless data compressor capable of handling multichannel electroencephalogram (EEG), electrocardiogram (ECG) and diffuse optical tomography (DOT) bio-signal data for reduced storage and communication bandwidth requirements in portable, wireless brain-heart monitoring systems used in hospital or home care settings. The compressor integrated in a multiprocessor brain-heart monitoring IC comprises 15 k gates and 12 kbits of RAM, occupying a total area of 58 k μm2 in 65 nm CMOS technology. Results demonstrate an average compression ratio (CR) of 2.05, and a simulated power consumption of 170 μW at an operating condition of 24 MHz clock and 1.0 V core voltage. Nominal power savings of 43% and 47% at the transmitter can be achieved when employing Bluetooth and Zigbee transceivers, respectively.

A low power biomedical signal processing system-on-chip design for portable brain-heart monitoring systems

In this paper, an overview of a brain-heart monitoring system is first given. The latest development in miniature brain-heart monitoring system for emerging health applications is highlighted. Finally, the development of a low power biomedical signal processing and image reconstruction SoC design is presented. The significance of this SoC is to enable practical developments of portable real-time brain-heart monitoring systems. The proposed architecture comprises a novel functional near-infrared (fNIR) diffuse optical tomography system for brain imaging, an independent component analysis (ICA) processor for electroencephalogram (EEG) signal analysis, and a heart rate variability (HRV) analysis processor for electrocardiogram (ECG) signal analysis. Biomedical signals acquired from front-end sensor modules are processed in real-time or bypassed according to user settings. The processed data or biomedical signals is then losslessly compressed and sent to a remote science station for further analysis and 3D visualization. The final SoC is fabricated in UMC 90nm CMOS technology.

Design of heart rate variability processor for portable 3-lead ECG monitoring system-on-chip

The worldwide population of people over the age of 65 has been predicted to more than double from 1990 to 2025. Therefore, ubiquitous health-care systems have become an important topic of research in recent years. In this paper, an integrated system for portable electrocardiography (ECG) monitoring, with an on-board processor for time-frequency analysis of heart rate variability (HRV), is presented. The main function of proposed system comprises three parts, namely, an analog-to-digital converter (ADC) controller, an HRV processor, and a lossless compression engine. At the beginning, ECG data acquired from front-end circuits through the ADC controller is passed through the HRV processor for analysis. Next, the HRV processor performs real-time analysis of time-frequency HRV using the Lomb periodogram and a sliding window configuration. The Lomb periodogram is suited for spectral analysis of unevenly sampled data and has been applied to time-frequency analysis of HRV in the proposed system. Finally, the ECG data are compressed by 2.5 times using the lossless compression engine before output using universal asynchronous receiver/transmitter (UART). Bluetooth is employed to transmit analyzed HRV data and raw ECG data to a remote station for display or further analysis. The integrated ECG health-care system design proposed has been implemented using UMC 90nm CMOS technology.

Time-frequency analysis of heart sound signals based on Hilbert-Huang Transformation

In this study, a method based on Hilbert-Huang Transformation (HHT) for time-frequency analysis of heart sound signals is presented. HHT is employed because most biomedical signals such as Electroencephalogram (EEG), Electrocardiogram (ECG) and heart sound signals are non-stationary signals. Heart sound signals recordings are often contaminated with the spike noise caused by the front-end circuits or measurement instruments in the real situations. A digital median filter is firstly employed to remove the spike noise of the heart sound signals. Then, the time series data are decomposed into several IMFs (Intrinsic Mode Function) using Empirical Mode Decomposition (EMD) algorithm. Hilbert transformation algorithm is utilized to acquire the instantaneous frequency for every IMF. Simulation results show that time-frequency domain analysis of heart sounds signals based on HHT algorithm is able to offer higher frequency resolution.

Secure medical information exchange with reversible data hiding

Exchange of medical information between hospitals is an essential part for medical treatments. In addition, security issues relating to electronic exchanges of information should also be concerned to protect the patients privacy and to help the treatments. In cooperation with the Health Level seven (HL7) standard, we employ reversible data hiding to further assist reducing the human errors during the exchange of information delivery. Reversible data hiding has attracted more and more attention in both researches and applications. We consider hiding part of the HL7 information into medical images at the encoder, and at the decoder, both the original image and HL7 information can be perfectly recovered. Simulation results demonstrate the superiority over existing schemes, and the effectiveness for practical applications.

A real-time processing flow for ICA based EEG acquisition system with eye blink artifact elimination

This paper presents a real-time processing flow for ICA based EEG acquisition system with eye blink artifact elimination. Since EEG signals are one of the feeblest physiological electrical signals, it is easily contaminated by artifacts. Previously, ICA was used to extract artifacts from an EEG data segment in a time period. After processing of ICA, automatic artifact detection and elimination are performed. After that, artifact free EEG signals are reconstructed. Recently, many kinds of EEG applications such as BCIs are proposed to control machines through EEG directly. In order to make BCIs more feasible and reliable, the EEG signals used for BCIs need to be acquired from human without artifacts in real-time. In this work, a real-time ICA algorithm, ORICA, is adopted. Since eye blink artifact dose the most significant harm to EEG signals, this work focus on the automatic eye blink artifact elimination and the algorithm used for eye blink artifact detection is sample entropy. With these algorithms and the real-time processing flow we proposed, processing result of each EEG raw data is finished in 0.25 s after each sample time. In the end of this paper, the method used to evaluate the performance of eye blink artifact elimination is provided. Real EEG signals are also processed and the operation results are shown to remove the eye blink artifacts exactly without misses.

An online recursive ICA based real-time multichannel EEG system on chip design with automatic eye blink artifact rejection

This paper presents an online recursive ICA (ORICA) based real-time multi-channel EEG system on chip design with automatic eye blink artifact rejection. Since EEG signals are very feeble, they are easy to be contaminated by artifacts. Among all artifacts, eye blink artifact dose the most significant harm to EEG signals. For acquiring artifact free EEG signals, ICA is a popular method for artifacts extraction. After extraction of ICA, eye blink artifacts are rejected to improve the reliability of EEG applications such as brain computer interfaces (BCIs). To promote the feasibility and convenience of BCIs, a real-time ICA algorithm, ORICA, is adopted in this system. With ORICA, the system immediately finishes each ICA result after each sample time. After each ICA result is generated, the automatic eye blink artifact rejection and inverse ICA are performed to acquire eye blink artifact free EEG signals in realtime. For system portability and high integration, a front-end interface of commercial IC, ADS1298 provided by TI, and Bluetooth interface, UART, are implemented. The system is designed used TSMC 90nm CMOS technology with 8 channels EEG processing in 128 Hz sample rate of raw data and consumes 8.56 mW at 50 MHz clock rate. The design methods of the proposed EEG system are provided in this paper. The performance and processing results of the system are also shown to reach 0.2532 s latency after each EEG sample time.

A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis

This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um2, and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

An EKG system-on-chip for portable time-frequency HRV analysis

This paper presents an EKG system-on-chip (SOC) for portable health care and home monitoring applications. The EKG system acquires three channel EKG from front-end circuits and includes functions such as beat detection, interval calculation, and time-frequency analysis of heart rate variability (HRV) in real-time. An HRV analysis engine has also been developed using Lomb periodogram for time-frequency power spectral density (PSD) analysis of heart rate. HRV analysis as well as raw data can be transmitted via Bluetooth to a cell phone or remote station through a UART interface.

A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.