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Dive into the research topics where Erik Paaske is active.

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Featured researches published by Erik Paaske.


IEEE Transactions on Information Theory | 1974

Short binary convolutional codes with maximal free distance for rates 2/3 and 3/4 (Corresp.)

Erik Paaske

A search procedure is developed to find good short binary (N,N - 1) convolutional codes. It uses simple rules to discard from the complete ensemble of codes a large fraction whose free distance d_{free} either cannot achieve the maximum value or is equal to d_{free} of some code in the remaining set. Farther, the search among the remaining codes is started in a subset in which we expect the possibility of finding codes with large values of d_{free} to be good. A number of short, optimum (in the sense of maximizing d_{free} ), rate-2/3 and 3/4 codes found by the search procedure are listed.


IEEE Journal of Solid-state Circuits | 1991

An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

Jens Sparsø; Henrik Jørgensen; Erik Paaske; Steen Pedersen; Thomas Rübner-Petersen

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required for interconnection. The processing elements are implemented in pairs that are connected to form a ring. In this way three-quarters of the interconnections are between neighbors. The ring structure is laid out in two columns and the interconnection of nonneighbors is routed in the channel between the columns. The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2- mu m CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V/sub DD/=4.75 V and T/sub A/=70 degrees C). The core of the chip (excluding pad cells) is 7.8*5.1 mm/sup 2/ and contains approximately 50000 transistors. The interconnection network occupies 32% of the area. >


IEEE Transactions on Communications | 1990

Improved decoding for a concatenated coding system recommended by CCSDS

Erik Paaske

The concatenated coding system recommended by CCSDS (Consultative Committee for Space Data Systems) uses an outer (255,233) Reed-Solomon (RS) code based on 8-b symbols, followed by the block interleaver and an inner rate 1/2 convolutional code with memory 6. Viterbi decoding is assumed. Two new decoding procedures based on repeated decoding trials and exchange of information between the two decoders and the deinterleaver are proposed. In the first one, where the improvement is 0.3-0.4 dB, only the RS decoder performs repeated trials. In the second one, where the improvement is 0.5-0.6 dB, both decoders perform repeated decoding trials and decoding information is exchanged between them. >


IEEE Transactions on Information Theory | 1990

Quasi-cyclic unit memory convolutional codes

Jørn Justesen; Erik Paaske; Mark Ballan

Unit memory convolutional codes with generator matrices, which are composed of circulant submatrices, are introduced. This structure facilitates the analysis of efficient search for good codes. Equivalences among such codes and some of the basic structural properties are discussed. In particular, catastrophic encoders and minimal encoders are characterized and dual codes treated. Further, various distance measures are discussed, and a number of good codes, some of which result from efficient computer search and some of which result from known block codes, are presented. >


IEEE Transactions on Communications | 1998

Forced sequence sequential decoding: a concatenated coding system with iterated sequential inner decoding

Ole Riis Jensen; Erik Paaske

We describe a new concatenated decoding scheme based on iterations between an inner sequentially decoded convolutional code of rate R=1/4 and memory M=23, and block interleaved outer Reed-Solomon (RS) codes with nonuniform profile. With this scheme decoding with good performance is possible as low as E/sub b//N/sub 0/=0.6 dB, which is about 1.25 dB below the signal-to-noise ratio (SNR) that marks the cutoff rate for the full system. Accounting for about 0.45 dB due to the outer codes, sequential decoding takes place at about 1.7 dB below the SNR cutoff rate for the convolutional code. This is possible since the iteration process provides the sequential decoders with side information that allows a smaller average load and minimizes the probability of computational overflow. Analytical results for the probability that the first RS word is decoded after C computations are presented. These results are supported by simulation results that are also extended to other parameters.


international symposium on information theory | 1995

Concatenated coding system with iterated sequential inner decoding

Ole Riis Jensen; Erik Paaske

We describe a concatenated coding system with iterated sequential inner decoding. The system uses convolutional codes of very long constraint length and operates on iterations between an inner Fano decoder and an outer Reed-Solomon decoder.


international symposium on information theory | 1994

Search methods for rate 1/N convolutional codes used in concatenated systems

Erik Paaske; Ole Riis Jensen

Different criteria for selection of good convolutional codes have been tested and the interesting conclusion is that the Viterbi bound on BER evaluated at a higher E/sub b//N/sub 0/ value is the best guide when selecting codes for use on low E/sub b//N/sub 0/ channels.<<ETX>>


IEEE Transactions on Information Theory | 1978

Further results on binary convolutional codes with an optimum distance profile (Corresp.)

Rolf Johannesson; Erik Paaske


First ESA Workshop on Tracking, Telemetry and Command#N# Systems | 1998

High Speed Viterbi Decoder Architecture

Erik Paaske; Jakob Dahl Andersen


IEEE Transactions on Very Large Scale Integration Systems | 1991

Design of a Fully Parallel Viterbi Decoder

Jens Sparsø; Steen Pedersen; Erik Paaske

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Jens Sparsø

Technical University of Denmark

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Jørn Justesen

Technical University of Denmark

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Steen Pedersen

Technical University of Denmark

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Jakob Dahl Andersen

Technical University of Denmark

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Knud J. Larsen

Technical University of Denmark

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Ole Riis Jensen

Technical University of Denmark

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Mark Ballan

University of Copenhagen

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