Steen Pedersen

An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders

Abstract Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements, but the storage elements must be provided with multiplexers on the input and they have a poor density compared to RA M cells. Furthermore, a rather complicated interconnection structure is required. The TBA requires more than three times as many storage elements, but these can be realized as RAM cells. A new algorithm which combines the advantages of both the REA and the TBA is proposed. It requires only slightly more storage elements than the REA and most of the storage elements can be realized as RAM cells. For a standard decoder with constraint length K = 7, rate R = 1 2 and decoding depth L = 56, significant area savings compared to the REA and the TBA are achieved. Furthermore, the relative area savings increase for larger decoding depths, which might be desirable for punctured codes. Based on the new algorithm a test chip has been designed and fabricated in a 2 micron CMOS process using MOSIS like simplified design rules. The chip operates at 20 Mbit/s. The core of the chip measures 3.5 × 8.1 mm2, and it contains approximately 50,000 transistors.

VRML visualization in a surgery planning and diagnostics application

In this paper we want to analyze how the high-level languages Java and VRML can be used for 3D medical imaging and simulation on a PC. We want to compare two different approaches to use Java combined with VRML. One approach is to use Java locally inside VRML (JSAI), the other is to control a VRML environment externally from Java (EAI). We also examine the usefulness of VRML animation used for surgery simulation.nFirst we describe a VRML centered application using Java for behavior processing through the JSAI script interface. This is done using the best publicly available browsers. This approach causes problems due to difficulties in handling the very complex models needed and in the limited Java support.nA second implementation is centered around a Java application, where the VRML browser is handled as a Java component. The VRML browser is controlled from Java through the EAI external application interface. VRML animation is used in both prototypes. We use our in-house developed VRML library Hybris for the second implementation, where we have full control over the VRML engine and rendering engine which allows better handling of larger models.

The importance of interfaces: a HW/SW codesign case study

This paper presents a codesign case study in image analysis. The main objective is to stress the importance of handling HW/SW interfaces more precisely at the system level. In the presented case study, there is an intuitive and simple HW/SW interface, which is based upon the functional modules in the application. However, it is found that this seemingly sound choice caused a number of practical problems and sub-optimal solutions during the implementation of the prototype system.

Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off

This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance requirement of this application is a frame rate of 25 frames per second when rendering 3D models with 2 million triangles, i.e. 50 million triangles per second, sustained (not peak). At present, a software implementation is capable of 3-4 frames per second for a 1 million triangle model. By using direct evaluation of certain interpolation parameters instead of forward differencing, writing back parameters to SDRAM is avoided. In software, forward differencing is usually better, but in this hardware implementation, the trade-off has made it possible to develop a very regular memory architecture with a buffering system, which can reach 95% bandwidth utilization using off-the-shelf SDRAM, This is achieved by changing the algorithm to use a memory access strategy with write-only and read-only phases, and a buffering system, which uses round-robin bank write-access combined with burst read-access.

A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network occupies 32 % of the area, and the global signals (including power) occupy a further 10 %. A test-chip containing a pair of processing elements has been fabricated via NORCHIP (the Scandinavian CMOS IC prototype implementation service). This chip has been fully tested, and it operates correctly at speeds above 26 MHz under worst-case conditions (VDD = 4.75 V and TA = 70 °C).