Erik Peeters

A capacitive pressure sensor with low impedance output and active suppression of parasitic effects

Abstract This paper describes the design, operating principles and performance of a capacitive pressure sensor in silicon, combined with a dedicated CMOS interface circuit. The readout circuit is designed to suppress parasitics and to yield an output signal proportional to pressure. The sensor-specific part is fabricated using standard photolithography, silicon micromachining in KOH, and anodic silicon/glass bonding at wafer level. The devices measure 2.2 × 3.5 × 0.8 mm and show a typical zero-pressure capacitance of 10 pF, with pressure-induced changes up to 250%. The interface chip ‘CAPRICE’ (CApacitive Pressure sensor Readout IC) is processed in a 3 μ n-well CMOS process and was designed to anticipate the intrinsic drawbacks of the capacitive transducing principle, i.e. sensitivity to environment noise, nonlinear output response and effects of parasitic capacitances. These drawbacks have always prevented the breakthrough of integrated capacitive mechanical sensors. CAPRICE, however, converts small capacitance variations into a noise-insensitive output voltage and a first-order linearisation is achieved by inversion of the hyperbolic capacitance versus pressure relationship. A second-order linearisation is obtained by the adoption of a novel suppression scheme for parasitic capacitances to the substrate. Parasitic capacitance rejection ratios up to 80 dB can be achieved in this way, enabling the practical feasibility of capacitive pressure sensors with less than 0.5% of full-scale nonlinearity.

Toward sub 1 V analog integrated circuits in submicron standard CMOS technologies

Lower channel lengths lead to lower supply voltages. For 0.25 /spl mu/m MOSTs the supply voltage is 2.5 V. Even lower supply voltages will follow. This paper deals with analog integrated circuits that can handle the reduction of the supply voltage down to 1 V. Existing solutions for such low supply voltages are: 1) reduction of threshold voltages from 0.7 V to 0.3-0.4 V; 2) use of voltage multipliers. It is possible to reduce supply voltages to 1 V in standard CMOS without voltage multipliers. The advent of deep submicron CMOS dictates reduced supply voltage.

A highly symmetrical capacitive micro-accelerometer with single degree-of-freedom response

A high-performance acceleration sensor concept is presented, which combines multiple wafer bonding and differential capacitance measurement into a fully symmetrical design. The main device characteristics are an exclusive response to a translational acceleration component in a single axis, a maximized sensitivity for a given chip area and a substantially improved linearity by suppression of error sources as fringing fields, stray capacitances, leakage resistances and electrostatic pressure. Modifiable damping characteristics and hence adjustable bandwidth is an additional device feature. The general concept, the main design considerations, the fabrication procedure and the performance of this new solid state acceleration sensor are discussed. The particular problem of gas flow damping at low pressures is addressed via SPICE simulation of electrical equivalent networks. Damping-relate distortion effects on dynamic range and bandwidth are demonstrated quantitatively.

An oscillator circuit for electrostatically driven silicon-based one-port resonators

Abstract This paper describes design considerations and characteristics of oscillator circuitry for electrostatically driven silicon-based one-port resonators, used as resonant strain gauges. The oscillation conditions for a general, single transconductance oscillator are theoretically derived. In order to start oscillation, guidelines to select proper bias conditions for the resonator are presented, taking the non-linear effects into account. An oscillator circuit has been designed in CMOS technology in order to verify the theory experimentally. Experimental results of the oscillator in combination with a silicon beam resonator are given.

PHET, an electrodeless photovoltaic electrochemical etchstop technique

A novel etchstop technique for the fabrication of micromechanical components in single-crystal silicon is presented. The photovoltaic electrochemical etchstop technique (PHET) was characterized for anisotropic etching in 7M KOH in the 60/spl deg/ to 80/spl deg/C temperature range, but can in principle be extended towards other anisotropic etchants. PHET is based on the photovoltage generated across a p/n junction illuminated during etching. In contrast with the established two-, three- or four-electrode electrochemical etchstop on n-epi, the technique does not require any external electrodes or connections to be made to the wafer, hence alleviating the need for a mechanical etchholder that protects one wafer side from the etchant. These etch-fielders are known to introduce stress and to substantially reduce yield in the production of the more fragile microstructures. Moreover, PHET is suited for the realization of diaphragm type structures in p-epi as well as for undercutting boron-diffused beam or bridge type of structures. In contrast with the established high boron dose etchstop, with its known adverse mechanical and electrical side effects, PHET does not require excessive boron concentrations. PHET therefore merges the fabrication possibilities offered by the conventional electrochemical etchstop and the conventional high boron dose etchstop, without being subject to the respective drawbacks of these techniques. The only technology required in addition to those used in the conventional etchstops is platinum sputtering. The possibilities that are offered for postprocessing standard p-well or twin-tub CMOS substrates are considered to be a major asset of the presented photovoltaic etchstop. >

A fully differential 1.5 V low-power CMOS operational amplifier with a rail-to-rail current-regulated constant-g/sub m/ input stage

This paper presents a compact fully differential amplifier with a rail-to-rail input stage and a class AB output stage. A new biasing scheme for a complementary rail-to-rail input stage with constant g/sub m/ is introduced. The proposed biasing scheme uses a current regulating loop to keep the sum of the biasing currents of the complementary input pairs constant. This results in a g/sub m/-variation below 4% for input pairs operating in weak inversion. In a standard 0.7 /spl mu/m CMOS technology the circuit can handle power supply voltages ranging from 1.5 V up to 3.3 V. For a power consumption of 300 /spl mu/W and a load capacitance of 15 pF a gainbandwidth (GBW) of 4.3 MHz is achieved. This results in a GBWCL-to-supply-power ratio of 210 MHz/spl middot/pF/mW. The total die area of the amplifier is 0.25 mm/sup 2/.

A combined silicon fusion and glass/silicon anodic bonding process for a uniaxial capacitive accelerometer

A high performance acceleration sensor concept is presented, which combines multiple wafer bonding and differential capacitance measurement into a point-symmetrical design. The accelerometer is a four-layer glass/Si/Si/glass structure realized with a combination of Si/Si fusion bonding and Si/glass anodic bonding. Fusion bonding with wafer-to-wafer alignment is performed on preprocessed silicon. Glass covers are bonded onto both wafer sides in a single anodic bonding sequence with polarity reversal. The main device characteristics are an exclusive response to a translational acceleration component in a single axis and maximized sensitivity for a given chip area. Modifiable damping characteristics and hence adjustable bandwidth is an additional device feature. This is obtained by controlling the gas pressure and composition during anodic bonding of the glass covers.

An implantable pressure sensor for use in cardiology

Abstract A miniaturized capacitive pressure sensor has been developed for implantation in the human heart. Since no d.c. current (max 10 μA) can be tolerated inside the heart for safety reasons, an a.c. measuring circuit is mandatory for this purpose. The sensor measures 2 mm × 2 mm and is sealed to a glass substrate by anodic bonding. For the a.c. mode of operation, a capacitive voltage divider and impedance converter have been designed and processed in a standard 3 μm CMOS process. The divider consists of the sensor capacitor and a reference capacitor, and the circuit is powered by an alternating voltage source. The pressure signal modulates the current in the power line. This results in a two-wire approach, with a low output impedance, in total absence of any d.c. components.

Test structures for HF characterization of fully differential building blocks

A procedure is described which allows us to characterize fully differential building blocks as a linear 4-port. A new set of linear differential hybrid parameters is presented which are well suited to describe fully differential amplifiers. A measurement setup is described which allows us to determine the differential h-parameters from measured S-parameters obtained with a 2-port test set. Measurement results of a 400 MHz fully differential amplifier are presented which demonstrate the new measurement procedure.

High-frequency measurement procedure for fully differential building blocks

A procedure is described which allows characterization of fully differential building blocks as a linear four-port. A new set of linear differential hybrid parameters is presented which is well suited to describe fully differential amplifiers. A measurement setup is described which allows determination of the novel differential h-parameters from measured s-parameters obtained with a two-port test set. Measurement results of a 400 MHz fully differential amplifier are presented which demonstrate the new measurement procedure.