Willy Sansen

A 12-bit intrinsic accuracy high-speed CMOS DAC

A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 /spl mu/m CMOS technology is presented. It is based on a current steering doubly segmented 6+2+4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSBs), respectively. The measured glitch energy is 1.9 pV.s. For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV.s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm/sup 2/.

Mismatch characterization of small size MOS transistors

A test chip for characterization of transistor mismatch in a standard 1.2 /spl mu/m CMOS technology is presented. A new algorithm for matching parameter extraction has been used. Mismatch parameters based on measurements on 12000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 1.2 /spl mu/m channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed.

Custom analog low power design: the problem of low voltage and mismatch

The never ending story of technology trends towards smaller transistor dimensions have resulted to date in deep submicron transistors. The consequence is the down scaling of the power supply voltages, to date even lower than 2 V, with almost the same threshold voltages of the CMOS transistors. Those low voltages mean that some widespread techniques such as switched-capacitors cannot be implemented anymore. On the other hand custom integrated circuits require continually higher speeds, more accuracy and less power drain. In the first section, the impact of mismatch or accuracy in analog circuits and the impact on power drain is discussed. Secondly, in section two some fundamental limitations of analog integrated circuit design in the trade-off between speed, accuracy and power drain are analysed. In the third section the problem of very low voltage signal processing in switched-capacitor circuits is studied. Some solutions, such as the switched-opamp technique are presented, and the technique is demonstrated by the design of a very low power, low voltage sigma delta modulator. The design and the measurements of 12 bit sigma delta AD converters running at 1.5 V power supply voltage and consuming less than 100 /spl mu/W in standard CMOS technology are finally discussed.

Mismatch Characterization of Submicron MOS Transistors

The characterization of transistor mismatch in a standard0.7 µm CMOS technology is presented. A new methodfor matching parameter extraction has been used. Mismatch parametersbased on measurements on 10000 nMOS and 10000 pMOS transistorshave been extracted. It is observed that the threshold voltagemismatch linear dependency on the inverse of the square rootof the effective channel area no longer holds for transistorsof 0.7 µm channel length. An extended model basedon the physical causes of threshold voltage mismatch is proposed.Contrary to the established theory, it is observed that transistorswith channel length below 1 µm have less currentmismatch than what is predicted by a linear relationship withthe channel area.

A high yield 12-bit 250-MS/s CMOS D/A converter

A 12-bit linearity binary-weighted all MOS transistor D/A converter is presented. Experimental results demonstrate the feasibility of fabricating with high yield such a converter in a standard CMOS 0.7 /spl mu/m technology. The output drives a doubly terminated 50 /spl Omega/ coaxial cable. The full scale 10-90% rise/fall time is 4 ns. The active chip area is 1 mm/sup 2/.

Matching of MOS transistors with different layout styles

A test chip with NMOS transistor pairs with different layout styles to study its influence on matching is presented. Common centroid structures are found to have much better matching performance than finger style structures. They show no systematic mismatch, and have a matching dependence on the channel area which is in agreement with measurement results on simple rectangle structures. Under die stress induced by packaging, finger style transistor pairs show a spread on transistor matching up to 5 times higher than the value predicted by only considering random fluctuation of the channel area.

A 12 bit 200 MHz low glitch CMOS D/A converter

A 12-bit 200 MHz CMOS current steering D/A converter is presented. The measured glitch energy is 0.8 pVs. To obtain this very low glitch energy specification, a new driver circuit using a dynamic latch is proposed. The measured INL is better than +/-0.5 LSB. The D/A converter operates at a 2.7 V power supply, it has a 20 mA full swing output current and a 200 MHz conversion rate. The worst case power consumption is 140 mW at the maximum conversion rate. The chip has been processed in a standard 0.5 /spl mu/m CMOS technology.

Influence of die attachment on MOS transistor matching

A test chip which allows the experimental study of the influence of die residual stresses on MOS transistor matching, in a standard 0.7 /spl mu/m CMOS technology, is described. The influence of eutectic die bonding on transistor matching is found to be a major degradation factor. Polyimide bonded dies do not significantly affect the matching performance of MOS transistors.

Statistics for matching

A statistical approach for evaluating the stochastic mismatching between two identically designed elements on the same chip is discussed. An approach to determine accurate matching parameters for a specific pair of devices and to obtain realistic worst case parameters for the area dependency model is presented. The approach is demonstrated by applying it to measured transistor threshold voltage mismatching data for a 0.7 /spl mu/m CMOS technology.