Erland Nilsson

Load Distribution with the Proximity Congestion Awareness in a Network on Chip

In networks on chip (NoC) very low cost and high performance switches are of critical importance. For a regular two-dimensional NoC, we propose a very simple, memoryless switch. In the case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the maximum tolerable load of the network, we propose a proximity congestion awareness (PCA) technique, where switches use the load information of neighbouring switches, called stress values, for their own switching decisions, thus avoiding congested areas. We present simulation results with random traffic which show that the PCA technique can increase the maximum traffic load by a factor of over 20.

Trading off power versus latency using GPLS clocking in 2D-mesh NoCs

To handle the design complexity when the number of transistors on-chip reaches one billion, new ways of organizing chips will be needed. One solution to this problem is to organize computational resources in a grid, where all communication between the resources are performed using an interconnection network. These networks are commonly referred to as networks-on-chip, or NoCs. This paper focus on the trade-off between power and latency while keeping the required interconnection bandwidth constant. The clock frequency can be lowered to reduce the power, with reduced bandwidth as a consequence, which in a synchronous system will increase the latency linearly. In a 2D-mesh NoC structure. It is possible to choose the regions with different clock phase and arrange them in such ways that the latency from sender to receiver along certain paths is nearly constant, and the total average latency is reduced with 50%. The reduction can then be exploited to trade off latency vs. power; the GPLS solution consumes 50% of the power compared to the fully synchronous solution, at the same latency and constant throughput.

Low-power and error coding for network-on-chip traffic

The goals of this paper are to explore adaptability of low-power coding techniques, and estimate error coding overheads for Network-on-Chip (NoC) bus interconnections. Our simulations show that bus invert encoding and partial bus invert encoding are not efficient due to their large overheads. On the other hand, implementation of error protection codes in the switch has only a small influence on both power consumption and time delay.