Ernest Wayne Balch

Characterization Of A Submicron Image Reversal Process

The complete characterization of a resist imaging process is critical to its success in a production environment. AZ-5214 resist in image reversal mode offers a single layer process that appears to be viable for submicron processing. It does, however exhibit some unique problems that had to be solved during process development. These are: 1) an extreme sensitivity to processing delays, 2) undercut profiles on reflective metal surfaces and 3) different dry etch characteristics. In this development effort the key advantages of image reversal were: reduced proximity effects, higher resolution, vertical resist profiles, as well as greater exposure latitude. AZ-5214 used in image reversal mode is very sensitive to any change in delay time during the processing sequence. In each case increased delay time causes growth in linewidth. This change in dimension is most significant right after the exposure and bake steps. The problem can be minimized by employing a stabilization time after softbake and exposure. Integrating the reversal bake, flood expose, and develop sequence in a single track is also necessary for consistent dimensional control. Negative tone processing of AZ-5214 resist exhibits undercut profiles at the resist metal interface. Metals with different reflectivity such as aluminum, moly, and Ti/W all demonstrate this problem. The use of anti-reflection layers provide vertical profiles at the expense of increased process complexity. Layers that have shown good results are PE/CVD nitride and PE/CVD oxide. The process characterization data includes: exposure and focus latitude for a range of feature sizes, proximity effect data for dense and isolated features, linewidth uniformity after etch, and dwell time latitude. Also included are the results of daily particle counts over a four month period.

Methods of Metal Patterning and Etching

Publisher Summary This chapter describes the methods of metal patterning and etching. Photolithography equipment and processes are available for use in the patterning of metallizations suitable for very-large-scale-integration applications where the critical dimensions are in excess of about 1.0 μ m. Improvements in equipment, photoresist materials, and the use of multiple layers and contrast enhancement materials may push the lower limits of optical lithography to the 0.5 μ m or lower. At the same time, electron beam and X-ray lithography are being improved with the goal of implementing submicron processes on a manufacturing scale. Dry etch techniques for pattern replication also have demonstrated capabilities in the 1.0 μ m range. Decreasing geometries and increasing wafer sizes, however, represent a combination that most likely requires the abandonment of batch etch systems in favor of single-wafer systems. Etch rate improvements, as well as more accurate and more responsive endpoint detection and control, and greater selectivity to both resist and substrate are important factors in etch equipment and process development.

Toward multifunctional optical integration: an adaptive lithographic method for patterning optical structures

A new method of interconnecting various optoelectronic components is discussed. Offset error up to 25 microns can be corrected to achieve single mode alignment accuracies. Several planar optical devices were photocomposed using the adaptive photolithographic method and these have been shown to perform with the desired characteristics.

Contrast Enhancement Materials. Effects Of Process Variables On Critical Dimension Control With Altilith Cem-420.

The effect of several key process variables on the litho-graphic performance of Altilith CEM-420 was investigated. Linewidth control in the resist image was measured by etching the substrate and electrically probing the resulting polysilicon lines with a Prometrix LithoMap LM20 system. Scanning electron microscopy was also used for some of the linewidth measurements over topography. The CEM-420 process was most effective when used in conjunction with an optimized photoresist process. We investigated lowering the resist softbake temperature and/or increasing the developer concentration. In each case the CEM-420 process performed better with the original processing conditions. Increasing the thickness of the CEM-420 layer improved linewidth control whether expressed as the change in critical dimension with change in exposure dose or as the ability to image different feature sizes at a given exposure dose. CEM-420 dramatically improved linewidth control over topography. Exposure times increased by a factor of between two and three with CEM-420. The effect of increasing exposure time on wafer throughput was miffimal. CEM-420 provided improved resolution with sodium, potassium, and metal-ion-free developers. Proximity effects were reduced with CEM-420. Modeling studies agreed with the exper-imental results showing increased exposure latitude for small feature sizes, improved resist profiles, and a reduction in the effect of standing waves.

High-density multimode photonic backplane

The development of a photonic backplane for high-speed and high-bandwidth communications is presented. This hybrid, multimode, multi-channel backplane structure contains both electrical and optical interconnects, suitable for next-generation high-speed servers with terabit backplane capacity. Removable and all-passively aligned high density interconnects on this backplane are achieved by polymer based optical waveguides with integrated micro-optics and VCSEL arrays on conventional printed circuit boards. The fabrication of this photonic backplane requires few additional steps outside a traditional board-manufacturing environment and is largely compatible with existing processes.

Design rules for the fabrication of binary half-tone masks used for MEMS and photonic devices

Gray scale lithography is becoming a popular technique for producing three-dimensional structures needed in fabricating photonics and MEMS devices. The structures are printed using a variable transmission mask to yield the required continuous tone intensity during image formation. In binary half tone imaging (i.e., BHT), the transmission through the mask is adjusted by varying the open area of sub-patterns. Design rules, fabrication tradeoffs and a layout methodology employing a novel primitive cell to aid in constructing the BHT masks are discussed Simulation is leveraged to tie the BHT design with expected imaging results. The overall process is exercised by fabricating a specific grayscale design for use in a photonic application. The BHT mask approach to gray scale lithography is a viable method to fabricate three-dimensional images offering MEMS and photonics communities a cost effective alternative to gray scale masks which rely on specialty materials and films.