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Dive into the research topics where Richard Joseph Saia is active.

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Featured researches published by Richard Joseph Saia.


Applied Physics Letters | 1984

Direct W–Ti contacts to silicon

S. S. Cohen; Manjin J. Kim; Bernard Gorowitz; Richard Joseph Saia; T. F. McNelly; G. Todd

We have studied the contact resistance in a metallization system that employs a direct contact between a tungsten–titanium alloy and shallow junctions in silicon. The values obtained in the present study are all within acceptable limits (<100 Ω μm2) for very large scale integration applications. The metal–silicon system has been subjected to moderate heat treatments, similar to those required in processing two‐level metallization schemes. No detrimental effects on the electrical properties of these contacts have been observed.


Journal of Adhesion Science and Technology | 1993

Studies on metal/benzocyclobutene (BCB) interface and adhesion

Kyung-Wook Paik; Herbert Stanley Cole; Richard Joseph Saia; John J. Chera

Interfacial characteristics such as chemical reaction, metal diffusion, and morphology were investigated for Cu/BCB, Cr/BCB and Ti/BCB structures. Using Auger and XPS depth profiling, the formation of titanium carbide and chromium oxide was confirmed at the metal/BCB interface. Annealing at 250°C for extended periods resulted in the diffusion of Cu, Cr and Ti into the BCB and subsequent formation of Cu-Si, CrSi2 and Ti-Si compound precipitates. The reaction is a thermal diffusion controlled process which is dependent on time and temperature. Ar sputtering treatment of BCB film before metallization was found to roughen the surface, resulting in metal spikes which penetrate into the roughened BCB film. However, the peel strength of metals on BCB was only about 177 g cm_1presumably due to the brittleness of the BCB film. The etch rates of the BCB film in a reactive ion etcher (RIE) and a plasma etcher were measured using Ar, O2, O2 + CF4, and O2 + SF6 gas mixtures. Faster etch rates were obtained when CF4 an...


Applied Physics Letters | 1984

Inhibition of acid etching of Pt by pre‐exposure to oxygen plasma

Manjin J. Kim; L. A. Gruenke; Richard Joseph Saia; S. S. Cohen

Platinum etching characteristics in aqua regia have been studied. It was found that prior exposure to an oxygen plasma inhibits the dissolution of platinum in aqua regia. Oxygen, far more abundant in the exposed platinum than in the unexposed platinum, plays a key role in forming an inhibition layer, such as PtO2, which prevents chlorine ion attack. This inhibition layer appears to retard platinum etching effectively in chlorine‐based etch solutions. The layer has been observed to form at a fast rate, and it is insensitive to the oxygen partial pressure in the plasma chamber. The insoluble characteristics of both the inhibited platinum and the platinum silicide in aqua regia make it feasible to form an unframed contact interconnection for applications of very large scale integration.


electronics packaging technology conference | 2003

Advanced 3-D stacked technology

Ray Fillion; Robert John Wojnarowski; Christopher James Kapusta; Richard Joseph Saia; K. Kwiatkowski; J. Lyke

Array sensors (e.g. focal plane array detectors) have densely aggregated cells to capture low energy levels that are converted into electrical signals. In hybrid assemblies, where focal plane arrays are bump-bonded to readout ICs, pixel density is being continually increased as processing and assembly technologies improve. Denser arrays, combined with extremely high frame rates (e.g. >106 frames/sec) create a formidable explosion in signal content. One approach to overcoming this issue is to move the signal processing closer to the array, minimizing the number of interconnects and the interconnect length the raw pixel signal outputs must travel prior to digitization, providing opportunity to buffer bursts (<64 frames) of high-rate collection sessions. One innovative approach to achieving this is to use 3D stacking of the pre-processing electronics for each pixel row directly behind the sensor array. This paper describes the development of a high density, 3D stacking technology that is being applied to an 8000-pixel array sensor cube that can eventually be scaled to mega-pixel densities through tiling.


IEEE Transactions on Advanced Packaging | 2002

Development of integral passive components for multilayer organic MCMs at millimeter wave frequencies

Anh-Vu Pham; Vikram Krishnamurthy; D. Bates; W. Marcinkewicz; B. Schmanski; Richard Joseph Saia; L. Sprinceanu

We present the design and development of Ta/sub 2/N thin-film resistors for the multilayer organic multichip module (MCM) at microwave and millimeter wave frequencies. The Ta/sub 2/N thin-film resistors are integrated directly onto multilayer Kapton films and achieve a resistivity of 12.5 /spl Omega//sq. to 25 /spl Omega//sq. Several Ta/sub 2/N thin-film resistor structures have been fabricated and electrically characterized up to 50 GHz to develop design rules for this process. For the first time, an ultra-wide band terminator has been developed and integrated on Kapton flex using Ta/sub 2/N thin-film resistors. The measured results of this circuit demonstrate a return loss of less than 20-dB over a 50-GHz bandwidth.


Workshop on MCM and VLSI Packaging Techniques and Manufacturing Technologies | 1994

3-D Stacking Using the GE High Density Multichip Module Technology

R.A. Fillion; Richard Joseph Saia; R.J. Wojnarowski; G.A. Forman; B. Gorowitz

To solve the interconnect and packaging problems associated with large distributed processing systems and of mass memory systems, the GE Corporate Research and Development Center has developed a 3-D stacked multichip module (MCM) technology. This technology uses, as building blocks, modules produced by the GE High Density Interconnect (HDI) embedded chip process. The fundamental features of this 2-D HDI polymer film overlay process, which are used to interconnect a number of chips within a common substrate, are extended to the interconnection of a number of multichip substrates. The 2-D HDI substrates with their essentially planar surface, and chips recessed beneath the interconnect structure, are ideally suited for direct 3-D stacking of one substrate upon another. The thermal path of the stack is directly through the substrate to the base of the stack. The substrate I/O connections are brought to the substrate edges for vertical connection within the stack. The multilayer lamination and thin film interconnect processes used to interconnect the chips, i.e. polyimide film dielectric, laser formed vias, and electroplated copper metallization, are then applied to one or more of the four edges of the stack. This paper will describe the basic 2-D HDI process and how it was extended to the 3-D interconnection of multichip substrates.


1988 Microlithography Conferences | 1988

Characterization Of A Submicron Image Reversal Process

Ernest Wayne Balch; Stanton Earl Weaver; Richard Joseph Saia

The complete characterization of a resist imaging process is critical to its success in a production environment. AZ-5214 resist in image reversal mode offers a single layer process that appears to be viable for submicron processing. It does, however exhibit some unique problems that had to be solved during process development. These are: 1) an extreme sensitivity to processing delays, 2) undercut profiles on reflective metal surfaces and 3) different dry etch characteristics. In this development effort the key advantages of image reversal were: reduced proximity effects, higher resolution, vertical resist profiles, as well as greater exposure latitude. AZ-5214 used in image reversal mode is very sensitive to any change in delay time during the processing sequence. In each case increased delay time causes growth in linewidth. This change in dimension is most significant right after the exposure and bake steps. The problem can be minimized by employing a stabilization time after softbake and exposure. Integrating the reversal bake, flood expose, and develop sequence in a single track is also necessary for consistent dimensional control. Negative tone processing of AZ-5214 resist exhibits undercut profiles at the resist metal interface. Metals with different reflectivity such as aluminum, moly, and Ti/W all demonstrate this problem. The use of anti-reflection layers provide vertical profiles at the expense of increased process complexity. Layers that have shown good results are PE/CVD nitride and PE/CVD oxide. The process characterization data includes: exposure and focus latitude for a range of feature sizes, proximity effect data for dense and isolated features, linewidth uniformity after etch, and dwell time latitude. Also included are the results of daily particle counts over a four month period.


MRS Proceedings | 1990

Studies on the Surface Modification of Benzocyclobutene(BCB) Film By Plasma Ions

Kyung Wook Paik; Richard Joseph Saia; John J. Chera

The etch rates of BCB film in a reactive ion etcher(RIE) were measured using Ar, O 2 , O 2 +CF 4 , and O 2 +SF 6 gas mixtures. Faster etch rates were obtained when CF 4 and SF 6 were added to oxygen, since the presence of atomic fluorine enhances the etch rate of organics, while also etching Si and SiO 2 formed by exposure to oxygen gas. Surface compositional changes on the BCB film were observed by XPS after plasma modification. Pure O 2 and O 2 +CF 4 plasma oxidized the carbo-siloxane linkage (C-Si-O) of the BCB, resulting in the formation of SiO 2 on the surface. The O 2 +SF 6 plasma, however, did not produce the surface SiO 2 , because of its faster Si and SiO 2 etch rates. Ar ion sputtering following the plasma modification, restored the surface chemical composition to a state similar to the initial BCB surface.


TRANSDUCERS 2007 - 2007 International Solid-State Sensors, Actuators and Microsystems Conference | 2007

Experimental Study of a Novel Silicon Carbide MEMS Ignition Device

Aaron Jay Knobloch; Richard Joseph Saia; Kevin Matthew Durocher; Kanakasabapathi Subramanian

This paper presents a robust, low power MEMS igniter built using low pressure chemical vapor deposited (LPCVD) polycrystalline Silicon Carbide films. The MEMS igniter design is based on a 5 mum thick, low stress membrane composed of doped and undoped SiC layers making up the resistive heaters and passivation layer respectively. Experimental tests using an optical pyrometer to measure temperature indicate that this igniter can achieve temperatures beyond 1400degC, with less than 10 W power input, and a time response of less than 0.1 sec. Reliability tests were performed to characterize the igniter behavior as a function of time and determine the lifetime of the devices. Lifetime of the igniter at temperatures greater than 1300degC was limited due to the growth of unstable crystobalite oxide layers resulting in membrane fracture. Reliability significantly improved when operation of the igniter was limited to temperatures below 1 100degC.


VLSI Electronics Microstructure Science | 1987

Methods of Metal Patterning and Etching

Bernard Gorowitz; Richard Joseph Saia; Ernest Wayne Balch

Publisher Summary This chapter describes the methods of metal patterning and etching. Photolithography equipment and processes are available for use in the patterning of metallizations suitable for very-large-scale-integration applications where the critical dimensions are in excess of about 1.0 μ m. Improvements in equipment, photoresist materials, and the use of multiple layers and contrast enhancement materials may push the lower limits of optical lithography to the 0.5 μ m or lower. At the same time, electron beam and X-ray lithography are being improved with the goal of implementing submicron processes on a manufacturing scale. Dry etch techniques for pattern replication also have demonstrated capabilities in the 1.0 μ m range. Decreasing geometries and increasing wafer sizes, however, represent a combination that most likely requires the abandonment of batch etch systems in favor of single-wafer systems. Etch rate improvements, as well as more accurate and more responsive endpoint detection and control, and greater selectivity to both resist and substrate are important factors in etch equipment and process development.

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