Ernesto Perea
STMicroelectronics
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Featured researches published by Ernesto Perea.
asian solid state circuits conference | 2006
Loic Joet; Alessandro Dezzani; Franck Montaudon; Franck Badets; Florent Sibille; Christian Corre; Laurent Chabert; Rayan Mina; Frederic Bailleuil; Daniel Saias; Frederic Paillardet; Ernesto Perea
A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-dBm IIP3. It is based on a discrete-time approach centering the baseband signal at half the sampling frequency. The receiver integrates Low-Noise Amplifier, filters and two 40-MHz sigma delta Analog to Digital Converters achieving a 12-bit resolution in 100 kHz.
international solid-state circuits conference | 2008
F. Montaudon; R. Mina; S. Le Tual; Loic Joet; D. Saias; Razak Hossain; F. Sibille; C. Corre; V. Carrat; E. Chataigner; Jerome Lajoinie; S. Dedieu; Frederic Paillardet; Ernesto Perea
This paper describes a fully integrated scalable discrete-time receiver based on a merged SC mixer, filter and SAR ADC meeting the requirements of IEEE 802.16e and 802.11b/g/n standards. Recent work has shown the use of SC-filtering techniques in radio receivers, where sampling is done early in the RX path. Such discrete-time architectures require an early anti-aliasing (AA) filter prior to sampling. Multiple AA and channel filters with decimation stages have been used to strongly attenuate alias and adjacent channels and to allow sampling of the signal at a reasonable rate at the ADC stage.IF amplifiers are necessary to drive ADC input stage. The direct-conversion receiver architecture proposed here is based on a fully-passive CMOS approach. It is composed of one transconductance LNA and a resistive attenuator.
international solid-state circuits conference | 2005
Ernesto Perea; Christian Enz
This session highlights two important RF trends: the integration of various devices above the IC together with advanced CMOS and BiCMOS circuits, and the design of high-frequency (60GHz to 110GHz) wideband communication circuits. On one hand, the design of wireless circuits including above-IC bulk-acoustic-wave (BAW) resonators and filters opens the door to highly-integrated transceiver architectures for multi-band and multi-standard applications. On the other hand, there is now confirmed interest in 60GHz circuits spurred in part by opening 7GHz of unlicensed bandwidth around 60GHz. This band was traditionally the domain of III-V compound semiconductors. However, aggressive scaling of CMOS technology, and the increasing capabilities of SiGe technology, make feasible the fabrication of highly-integrated CMOS or SiGe mm-wave circuits for data-communication applications.
Archive | 1999
Ernesto Perea; Guillermo Bomchil; Aomar Halimaoui
Archive | 1999
Guillermo Bomchil; Aomar Halimaoui; Ernesto Perea; アーネスト・ペレア; アゥマー・ハリマオイ; ギジョム・ボンシル
international solid-state circuits conference | 2008
Christian Enz; Ernesto Perea; Ken Cioffi
international solid-state circuits conference | 2008
Albert J. P. Theuwissen; Roland Thewes; Ernesto Perea
international solid-state circuits conference | 2008
Albert J. P. Theuwissen; Roland Thewes; Ernesto Perea
international solid-state circuits conference | 2007
Albert J. P. Theuwissen; Ernesto Perea
international solid-state circuits conference | 2004
Ernesto Perea; T. Sakurai