Erwine Pargon

Pulsed high-density plasmas for advanced dry etching processes

Plasma etching processes at the 22 nm technology node and below will have to satisfy multiple stringent scaling requirements of microelectronics fabrication. To satisfy these requirements simultaneously, significant improvements in controlling key plasma parameters are essential. Pulsed plasmas exhibit considerable potential to meet the majority of the scaling challenges, while leveraging the broad expertise developed over the years in conventional continuous wave plasma processing. Comprehending the underlying physics and etching mechanisms in pulsed plasma operation is, however, a complex undertaking; hence the full potential of this strategy has not yet been realized. In this review paper, we first address the general potential of pulsed plasmas for plasma etching processes followed by the dynamics of pulsed plasmas in conventional high-density plasma reactors. The authors reviewed more than 30 years of academic research on pulsed plasmas for microelectronics processing, primarily for silicon and conductor etch applications, highlighting the potential benefits to date and challenges in extending the technology for mass-production. Schemes such as source pulsing, bias pulsing, synchronous pulsing, and others in conventional high-density plasma reactors used in the semiconductor industry have demonstrated greater flexibility in controlling critical plasma parameters such as ion and radical densities, ion energies, and electron temperature. Specifically, plasma pulsing allows for independent control of ion flux and neutral radicals flux to the wafer, which is key to eliminating several feature profile distortions at the nanometer scale. However, such flexibility might also introduce some difficulty in developing new etching processes based on pulsed plasmas. Therefore, the main characteristics of continuous wave plasmas and different pulsing schemes are compared to provide guidelines for implementing different schemes in advanced plasma etching processes based on results from a particularly challenging etch process in an industrial reactor.

Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas

We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition.

Reducing damage to Si substrates during gate etching processes by synchronous plasma pulsing

Plasma oxidation of the c-Si substrate through a very thin gate oxide layer can be observed during HBr/O2/Ar based plasma overetch steps of gate etch processes. This phenomenon generates the so-called silicon recess in the channel and source/drain regions of the transistors. In this work, the authors compare the silicon recess generated by continuous wave HBr/O2/Ar plasmas and synchronous pulsed HBr/O2/Ar plasmas. Thin SiO2 layers are exposed to continuous and pulsed HBr/O2/Ar plasmas, reproducing the overetch process conditions of a typical gate etch process. Using in situ ellipsometry and angle resolved X-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess can be reduced from 4 to 0.8 nm by pulsing the plasma in synchronous mode.

Linewidth roughness transfer measured by critical dimension atomic force microscopy during plasma patterning of polysilicon gate transistors

With the continuous scaling down of the critical dimensions (CDs) of semiconductor devices, the linewidth roughness (LWR) becomes a non-negligible parameter that needs to be controlled within 1nm (at 3σ) for the 32nm node and beyond. In this article, the authors have used a CD-atomic force microscopy to investigate the evolution of the LWR during the subsequent lithography and plasma etching steps involved in the patterning of polysilicon transistor gates. The authors demonstrate that the LWR present on the etching mask [photoresist/bottom antireflective coating (BARC), SiO2 or amorphous carbon hard masks] right before the gate etching is transferred into the polysilicon during the HBr∕Cl2∕O2 gate etching step. Thus, the final polysilicon LWR directly is strongly dependent on the lithography and plasma etching steps preceding the gate etching step. The authors show that by applying plasma treatment to minimize the resist mask LWR prior to all the other etching steps or by optimizing the BARC opening plasm...

Plasma impact on 193 nm photoresist linewidth roughness: Role of plasma vacuum ultraviolet light

193 nm photoresist patterns printed by optical lithography are known to present significant linewidth roughness (LWR) after the lithographic step that is partially transferred into the underlayers during plasma etching processes. In this study, we identify the factors that impact the photoresist pattern sidewalls roughness during plasma exposure. Among them, plasma vacuum ultraviolet light (110–210 nm) is shown to be the main contributor to the LWR decrease induced by plasma etching processes. In this paper, we also demonstrate the strong correlation between LWR obtained after plasma exposure and the surface roughening mechanisms taking place on top of the resist patterns.

Etching mechanisms of HfO2, SiO2, and poly-Si substrates in BCl3 plasmas

BCl3 based plasmas exhibit promising plasma chemistries to etch high-k materials and, in particular, HfO2, with a high selectivity over SiO2 and Si substrates. The authors report on the mechanisms involved in the etching of HfO2, SiO2, and poly-Si substrates in BCl3 plasmas. X-ray photoelectron spectroscopy analyses help in understanding the mechanism driving the high etch selectivity between HfO2 and silicon-containing substrates. The ion energy plays an important role in the etching mechanisms since it controls a transition between a BCl-like deposition on the substrate and its etching by ionic bombardment. The ion energy threshold above which etching occurs is different from one substrate to another, being lower for HfO2 than for Si substrates. Indeed, BClx deposition forms more easily on poly-Si or SiO2 rather than on HfO2 surfaces, because boron reacts with Si atoms to form Si–B bonds initiating the growth of BClx polymer on Si-containing surfaces, while on HfO2 surfaces, boron is directly involved i...

Monitoring chamber walls coating deposited during plasma processes: Application to silicon gate etch processes

During plasma etching processes, organic or mineral layers are deposited on the chamber walls. In general, these layers cause large and uncontrolled shifts in the etch process, which is becoming a major issue in some of the plasma processes used in integrated circuit fabrication. The chemical nature of these layers and their deposition mechanisms remain poorly understood due to the lack of in situ surface diagnostics available to monitor the reactor walls. In this article, we present a simple technique using x-ray photoelectron spectroscopy (XPS) analyses to monitor the chemical composition of the layer deposited on a sample floating on top of a 200-mm-diam wafer where the layers deposited are identical to those deposited on the chamber walls. The principle of the technique is to stick a small Al2O3 sample onto the 200-mm-diam silicon wafer, with an air gap between the sample and the wafer. Providing that the air gap is thick enough, the Al2O3 surface will be electrically floating even when the silicon wa...

Towards a controlled patterning of 10 nm silicon gates in high density plasmas

This article demonstrates that a 10 nm isolated silicon pattern on a very thin gate can be achieved if the plasma parameters and chemistry that impact the critical dimension (CD) control are well understood. The parameters investigated are the passivation layers that form on the silicon gate sidewalls which directly impact the CD control, the nature of the mask used during the gate process (resist mask or SiO2 hard mask), the charging effects developed when the plasma lands on a thin gate oxide.

Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning

The present work focuses on the line width roughness (LWR) transfer and the critical dimension control during a typical gate stack patterning and shows the benefits of introducing 193 nm photoresist treatments before pattern transfer into the gate stack to improve process performance. The two investigated treatments (HBr plasma and vacuum ultra violet (VUV) plasma radiation) have been tested on both blanket photoresist films and resist patterns to highlight the etching and roughening mechanisms of cured resists. Both treatments reinforce the etch resistance of the photoresist exposed to fluorocarbon plasma etching process used to open the Si-ARC (silicon antireflective coating) layer. The etch resistance improvement of cured resists is attributed to both the decrease in oxygen content within the resist and the crosslinking phenomena caused by VUV radiation during the treatment. As the magnitude of the surface roughness is directly correlated to the etched thickness, cured resists, which are etched less rapidly, will develop a lower surface roughness for the same processing time compared to reference resists. The LWR evolution along the pattern sidewalls has been studied by critical dimension atomic force microscopy during the Si-ARC plasma etching step. The study shows that the LWR is degraded at the top of the resist pattern and propagates along the pattern sidewalls. However, as long as the degradation does not reach the interface between resist and Si-ARC, the LWR decreases during the Si-ARC etching step. As resist pretreatments reinforce the resist etch resistance during Si-ARC etching, the LWR degradation along the sidewalls is limited leading to minimized LWR transfer. The LWR decrease observed after plasma etching has been explained thanks to a spectral analysis of the LWR performed by critical dimension scanning electron microscopy combined with the power spectral density fitting method. The study shows that the high and medium frequency components of the roughness (periodicity below 200 nm) are not totally transferred during the gate patterning allowing a LWR decrease at each plasma step.

Silicon recess minimization during gate patterning using synchronous plasma pulsing

With the emergence of new semiconductor devices and architectures, there is a real need to limit plasma induced damage. This study clearly demonstrates the capability of pulsed plasma technology to minimize plasma induced silicon oxidation that leads to the silicon recess phenomenon during polysilicon gate patterning. Indeed, the authors show that by pulsing optimized continuous wave overetch plasma conditions using HBr/He/O2 plasmas, the silicon recess is reduced from 0.6 to 0.2 nm, while the gate profiles are maintained anisotropic. Synchronous pulsed plasmas open new paths to pattern complex stacks of ultrathin materials without surface damage.