Nicolas Posseme

Impact of Downstream Ash Plasmas on Ultra Low-k Materials

Introduction Next generation integrated circuits require novel materials with a dielectric constant lower than 2.5. To lower the dielectric constant, porous Methyl-SilsesQuioxane (MSQ) materials are introduced with a k value of about 2.2. The integration of these materials presents new processing issues, mainly due to a change in material density caused by the presence of the pores [1]. For instance, ash treatments for photoresist and residues removal are critical steps leading to dielectric properties modifications [2]. In this paper, we present the structure and properties modifications of porous and non-porous MSQ films under various downstream ash processes.

Enabling the use of ion implantation for ultra-thin FDSOI n-MOSFETs

For the first time, we extensively review to which extent ion implantation is viable for the design of n-FET transistors with gate length down to 20nm in a FDSOI technology. Three implantation schemes are covered and their potential and limitations are presented in terms of technological challenges and electrical performance.

Implant approaches and challenges for 20nm node and beyond ETSOI devices

Two implantation based schemes were explored for ETSOI NFET devices targeted for the 20nm node. Amorphization of the thin SOI is a key issue for the implant pre RSD scheme. This can be alleviated by implanting through liner. Variability is the key issue for the implant post RSD scheme which can be alleviated by good process controls and by the use of a two step epitaxy scheme.

Ellipsometry measurements on ultrathin silicon on insulator films

For silicon thickness measurements by ellipsometry, if a high precision is required, i.e. if the thickness has to be known better than 10%, use of an optimized model becomes mandatory. The improvement of the model is consistent with previous measurements which were interpreted as evidence for room temperature quantum confinement effects.

Enabling epitaxy on ultrathin implanted SOI

In Fully Depleted Silicon On Insulator (FDSOI) transi stors, the channel thickness is being scaled down with the gat length to insure a good electrostatic control of the gate ove r th channel. Typically for the 20nm node, the transistor integri ty is maintained by keeping the channel thickness below 6nm [1]. Thi s downscaling raises several technological challenges , especially when using an integration scheme in which extensions are implanted before the Raised Source and Drain (RSD) growth (Fig. 1). The challenge lies in finding a viable tradeoff between amorphization and high dopant concentration within t e film. In this paper we present what are the main physical lim itations when implanting the SOI, as well as an efficient way to a lleviate them.

Study of Resist Strip Chemistries for Ultra Low-k/Cu Interconnect

New generation of integrated circuits requires the introduction of ultra low-k dielectric material (k < 2.5) to reduce the RC delay. One of the challenges in integrating these ultra low-k materials is the susceptibility of porous dielectric materials to the post etch resist stripping and residue clean processes. There have been studies comparing the effect of oxidization and reducing chemistries to the ultra low-k materials in a conventional asher [1]. There has also been report on the approach of using directional ashing to avoid damage to the ultra low-k materials [2]. In order to gain further understanding regarding the effect of oxidizing vs. reducing chemistries, ion vs. radicals, pressure and temperature to the low-k materials (both dense and porous), we have started a comprehensive study to find answers to these questions. This paper is to report our initial data from this effort.