Etienne Tisserand

Parallel architecture dedicated to connected component analysis

This paper presents the design of a dedicated parallel architecture for connected component analysis. Categorized in one-dimensional array processors, for an image of n/spl times/n pixels, the proposed architecture has n-1 linear processing elements (PEs), n/sup 2/ CAM memory modules, and a tree structure of (n/2)-1 switches allowing communication through the global bus in O(log n) unit of propagation time. Well suited for low and intermediate-level vision, this architecture allows sequential processing through its line structure which is perfectly adapted to real time image analysis from any interlaced-mode video signal. This paper presents the algorithms for connected component labeling, area and perimeter determination, all of which are in O(n log n). The performance of the proposed architecture is compared with another architecture types. The simulation results, the possibility of implementation, and future work are discussed.

Arc Fault Analysis and Localisation by Cross-Correlation in 270 V DC

This article is focused on low-frequency, spectral and correlation analysis to serial arc fault electrical system in order to detect arc fault. This analysis can be used to improve the security of power supplies in the automotive, aerospace and photovoltaic systems. More precisely, we study the influence of arc ignition on the signal characteristics. The experimental test bench is composed by an arc generator, a robotic cylinder and different loads. Three types of arcs ignitions are considered: carbonized path, contact opening and over-voltage. 0.5 kHz - 500 kHz spectrum is measured before and during the start phase of the arc and stabilization. The results show the possibility to determine the cause of the arc fault ignition. The shape of low frequency arc voltage is estimated from the current measurement with a very high fidelity where the load is known. Finally we study the possibility to locate series arcs by analyzing the correlation function of the Radio Frequency (RF) signals from two Rogowski coils inserted at two distinct points of the circuit. The calibration procedure performed reveals a mean velocity in the system of about 24 cm/ns.

Frequency Analysis to Arcing Detection and Prototyping FPGA Approach

Several authors propose different methods to arc fault detection based on time or frequency characteristics. Among those, some papers present the arcing fault detection using a specific frequency band on the current or voltage. This paper presents an overview of the different frequencies bands proposed by the authors that allow the detection of an arcing fault. To compare these proposed methods, we make a frequency analysis to obtain the frequencies characteristics of arcing fault for different loads signatures (resistive, inductive and nonlinear load). The method we have developed for arcing detection are based on five criterions: Analysis of the current low frequency, the voltage high frequency, the 5th harmonic current and current and voltage magnitude variations. Hardware in the loop approach allows us to test the methods of detection. Finally, our architecture of arcing detection is implemented on Field Program Gate Array (FPGA) prototyping board.

Ultrasonic scattering technique for target size measurement

We present in this paper a new ultrasonic method for sizing immersed wires (or more generally any kind of target shape). By extracting the first part of its backscattered echo, which gives what we call the quasi-rigid backscattered echo (QRBE), the size of a wire can be found by comparing its QRBE spectrum with the quasi-rigid form function (QRFF). The principal advantage of the QRFF in comparison with the form function is to be almost insensitive to the targets acoustical properties. After some theoretical aspects, we present step by step our sizing method using ultrasonic scattering. Some experimental results of wire sizing are presented.

Modeling of an ultrasonic auto-controlled frequency generator in VHDL-AMS language

In this paper, we present the structure of digital generator feedback which is controlled for the optimal excitation of ultrasonic high efficiency narrow band transducers. In the first phase, simulations allow various excitation signal forms to be compared in terms of efficiency. A burst of sine waves has been selected because there is no excitation of the transducers harmonic and anharmonic resonances. In order to exploit this type of excitation without knowing the central frequency of the transducer, we propose that the generators architecture includes an automatic search of the antiresonance frequency of a piezoelectric ceramic. Our strategy is based on studying the electric voltage at the transducers output, and the iterative algorithm we have developed looks for the maximum value of this voltage which is validated by a modeling in VHDL-AMS language (IEEE standard 1073–1993), including the transducer. We present the results of modeling in terms of the time setting and the frequential precision obtained with two different piezoelectric ceramics.

Arc fault detection based on temporal analysis

This article describes arc faults detection methods based on the temporal analysis of electric lines current signatures. We first give the, specifications of the domestic loads under test. Then, we describe the methods under test: crest factor, average value, variance, adaptive filter and mathematics moments. In the second part, these methods are implemented on MATLAB - Simulink. The analysis is done on the current for each period half cycle. The ability of arc faults detection is then presented for each algorithm.

Method to Design Arc Fault Detection Algorithm Using FPGA

Abstract-The object of this paper is to present a method to design and to improve arc fault detection algorithm using FPGA devices. When designing an arc fault detection prototype, criteria such as detection reliability, detection speed and silicon occupation must be extracted to compare detection algorithm performances. We have developed a device which can execute and test the performances of algorithms with differents kind of power sources (AC and DC for domestic and aeronautic applications) and any loads. This prototype includes an analog part to carry out line voltage and current measurements (up to 270 V, up to 50 A, up to 1.5 MSPS). The digital part is built with an Altera Cyclone III FPGA circuit. An interface is added to control a contactor which protects the electric line. Algorithm implementation is carry out with VHDL We describe the algorithms in VHDL. The board architecture is characterized by low power consumption, high fonctionality and fast prototyping. Our prototype gives an effective and inexpensive means to design arc fault detection algorithms.

Modeling of a Domestic Electrical Installation to Arc Fault Detection

Our work concerns the modeling of a typical electrical home installation which includes the electrical power supply, typical loads and also series and parallel arc faults. In this article, we present the models, developed under Matlab/Simulink, of the power supply, two different loads (vacuum cleaner and kettle) and an arc in series on the electrical line. The comparison between these models and real electric signals was done using harmonic analysis. Experiments were made to measure current and voltage signature of typical loads in different configurations (simple and combined load). The simulation results are in good agreement with the real signatures. In order to design an arc fault circuit breaker we propose then a Hardware-In-the-Loop (HIL) simulation approach. This allows us to validate the real functioning of a numerical detection algorithm by exploiting the models of the electric system to be protected. Also we show the first test results of an algorithm based on a frequential analysis for arc fault detection, using the HIL strategy.

Real-Time Connected Component Labeling on One-Dimensional Array Processors based on Content-Addressable Memory: Optimization and Implementation

Publisher Summary Connected component labeling is not easy to process because of its local and global features. These features make the labeling operation extremely time costly as sequential architecture has to be used because of its local operation principle. To reduce the processing time, labeling should be done in parallel using the local and global operations. This solution is very expensive, particularly for two- or three-dimensional array processors. To find a trade-off between processing time and hardware cost, this chapter proposes an efficient parallel architecture dedicated to connected component labeling based on content-addressable memory (CAM). For an n x n image, the optimized architecture merely requires n/2 -1 PEs and n 2 /4 CAM modules through a 4-pixels grouping technique. The algorithm proposed by the chapter, based on a divide-and-conquer technique, leads to a complexity of O(n log n) with a small multiplicative constant factor of an order of ½. The global communication is reconfigurable and ensured in O(log n) units of propagation time by a tree structure of switches. Hence, through this performance, this architecture reaches a quasi-optimal processor time in labeling. Moreover, the architecture permits sequential processing, perfectly adapted to labeling in one scan image from any interlaced-mode video signal.

Repeatable and calibrated arc fault generator

This article describes the design and use of a repeatable and calibrated arc fault generator. We have developed a test bench which can generate AC and DC currents and series and parallel arc faults on variable loads and have chosen a method which consists in producing an overvoltage in arc initiation, obtained with a step-up transformer; a line generator (AC or DC) then sustains the arc. We show the initial measurement results relating to arc current/voltage characteristics for all possible scenarios, thus enabling us to extract those indicators which are useful for fault detection (such as, for example, arc time constant). This device can also be used to test the arc fault detectors.