Yves Berviller

Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system

Abstract In this paper we present a new temporal partitioning methodology used for the data-path part of an algorithm for the reconfigurable embedded system design. This temporal partitioning uses an assessing trade-offs in time constraint, design size and field programmable gate arrays device parameters (circuit speed, reconfiguration time). The originality of our method is that we use the dynamic reconfiguration in order to minimize the number of cells needed to implement the data-path of an application under a time constraint. Our method consists, by taking into account the used technology, in evaluating the algorithm area and operators execution time from data flow graph. Thus, we deduce the right number of reconfigurations and the algorithm partitioning for Run-Time Reconfiguration implementation. This method allows avoiding an oversizing of implementation resources needed. This optimizing approach can be useful for the design of an embedded device or system. Our approach is illustrated by various reconfigurable implementations of real time image processing data-path.

A new ADPLL architecture dedicated to program clock references synchronization

This paper presents a totally digital phase locked loop (PLL) used for the recovery of a MPEG-2 decoder clock. The All Digital PLL (ADPLL) is implemented with a frequency synthesizer based on a new technique for phase shifting, avoiding the phase accumulation of ADPLL using a ring oscillator or avoiding the multiphase generation if a delay-locked loop (DLL) is used. The strongest point of the proposed configuration is the possibility of implementing as many ADPLLs as needed in a single circuit, in the limit of the circuit resources, without additional external circuit. The transfer characteristic, frequency resolution and jitter performance are computed and discussed. Then, the ADPLL resources and the ADPLL performances in term of time response and jitter are reported.

A partitioning methodology that optimises the area on reconfigurable real-time embedded systems

We provide a methodology used for the temporal partitioning of the data-path part of an algorithm for a reconfigurable embedded system. Temporal partitioning of applications for reconfigurable computing systems is a very active research field and some methods and tools have already been proposed. But all these methodologies target the domain of existing reconfigurable accelerators or reconfigurable processors. In this case, the number of cells in the reconfigurable array is an implementation constraint and the goal of an optimised partitioning is to minimise the processing time and/or the memory bandwidth requirement. Here, we present a strategy for partitioning and optimising designs. The originality of our method is that we use the dynamic reconfiguration in order to minimise the number of cells needed to implement the data path of an application under a time constraint. This approach can be useful for the design of an embedded system. Our approach is illustrated by a reconfigurable implementation of a real-time image processing data path.

Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation

In this paper, we present a method to estimate the number of reconfiguration steps that a time-constrained algorithm can accommodate. This analysis demonstrates how one would attack the problem of partitioning a particular algorithm into pieces to for run time reconfiguration execution on a Atmel 40K FPGA. Our method consist in evaluating algorithm operators execution time from data flow graph. So, we deduce the reconfiguration number and the algorithm partitioning for RTR implementation. The algorithm used in this work, is a qualitative motion estimator in the Log-Polar plane.

Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis

This article describes the theoretical principles and an original microelectronics architecture of a configurable conceptual decoder able to process a MPEG-2 DVB-T stream in real time (T-STD). The proposed hardware architecture allows to continuously measure the quality of service of the MPEG-2 stream component. The architecture has been modelled, validated and simulated by using the SystemC language in combination with real MPEG-2 DVB-T streams. It is composed of several modules allowing to model the various buffers of the T-STD parts (video, audio or system). Real time errors flags are generated when the buffers filling level becomes illegal (overflow, empty buffer, transfer delay). A VHDL model allows an implementation on the FPGA circuit Altera APEX20KE600. The hardware implementation of the configurable T-STD requires 9738 logical cells (LCs) and 12 kB of external memory.

FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T

The MPEG-2 DVB Transport Stream domain carries in addition to audio and video data a Program Clock Reference(PCR). This PCR is used to synchronize the MPEG-2 decoder clock on the receiver side for a given program. The PCR values can be affected by an offset inaccuracy due to encoder imperfection or by the network jitter. The measurement of different PCR parameters like drift, precision and jitter are necessary for evaluating the decodability efficiency. These measurements are generally achieved using a Phase Lock Loop and a set of measurement filters as it is recommended in the DVB-T QoS measurement standard. In this paper, we propose a FPGA implementation of an all digital PLL and its associated measurement filters. We demonstrate how it is possible to process all available programs in a DVB-T transport stream by using an FPGA with an associated embedded processor.

An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis

The MPEG transport stream is an extremely complex structure using interlinked tables and coded identifiers to separate the programs and the elementary streams. Quality management is therefore a complicated issue and the need to identify the degree of coding degradations in terms of coding and/or transmission errors or system failures is becoming an important criterion for the evaluation of the quality of the MPEG streams. A theoretical decoder (T-STD) defines the verification process based on the proper fill level of an MPEG decoder buffers whose size is defined by the standards in order to obtain an evaluation of the MPEG stream quality. This paper describes a new embedded and programmable solution capable of analysing MPEG streams in real time. The proposed hardware architecture provides a real time continuous buffer analysis of the MPEG stream components and is composed of several modules allowing for simultaneous modeling of the various buffers of the T-STD components (video, audio or system). Real time errors flags are generated when the buffers filling level becomes illegal (overflow, empty buffer, transfer delay, etc.). The architecture has been modeled, validated and simulated using the SystemC and VHDL languages in combination with real MPEG DVB-T streams. A VHDL synthesisable model of our architecture allows an implementation on an field-programmable gate array circuit based on Altera APEX20K1000. The hardware implementation of this configurable T-STD allows a data rate of 232 Mbps and requires only 9738 logical cells and 4,7 kB memory.

Automated RTR temporal partitioning for reconfigurable embedded real-time system design

We present an automated temporal partitioning applied on the data-path part of an algorithm for reconfigurable embedded system design. This temporal partitioning, included in a design space exploration methodology, uses trade-offs in time constraint, design size and FPGA device parameters (circuit speed, reconfiguration time). The originality of this partitioning is that it minimizes the number of cells needed to implement the data-path of an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resources needed. This optimizing approach can be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field.

Hardware partitioning software for dynamically reconfigurable SoC design

CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibilities of reconfiguration that the FPGA component can offer. Here, we present a temporal hardware partitioning software, included in a design methodology that uses the reconfiguration possibilities of the FPGA for the SOC system design. This automated partitioning tool minimizes the number of cells needed to implement an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resource needs. It can also be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field.

FPGA-based architectures of finite radon transform for medical image de-noising

This paper presents the design and implementation of finite Radon transform (FRAT) on field programmable gate array (FPGA). To improve the implementation time, Xilinx AccelDSP, a software for generating hardware description language (HDL) from a high-level MATLAB description has been used. FPGA-based architectures with three design strategies have been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)-based approach. Various medical images modalities have been deployed for both software simulation and hardware implementation. An analysis on the image de-noising using the FRAT is addressed and demonstrates a promising capability for medical image de-noising. Moreover, the impact of different block sizes on reconstructed images has been analysed. Furthermore, performance analysis in terms of area, maximum frequency and throughput is presented and reveals a significant achievement.