Eugene Grayver

Design and VLSI implementation for a WCDMA multipath searcher

The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 /spl mu/m CMOS technology and requires only 150 k gates for a total area of 1.5 mm/sup 2/ consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator.

Dual antenna UMTS mobile station transceiver ASIC for 2 Mb/s data rate

A silicon implementation of a dual antenna mobile station modem for 3G WCDMA is presented. Diversity processing is used to support data rates up to 2 Mb/s while reducing power consumption. An average SNR improvement of 7 dB has been observed yielding up to a 4x increase in capacity with no change to the exisiting network infrastructure.

Design and Implementation of a Baseband WCDMA Dual-Antenna Mobile Terminal

The design and implementation of a baseband wide-band code-division multiple access (WCDMA) dual-antenna mobile terminal system-on-a-chip (SoC) is presented in this paper. Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity. The SoC integrates the baseband transceiver, coding and decoding functions, microcontrollers to implement the radio access protocols, and external interfaces to communicate with the application layer. The receiver design, which takes advantage of diversity benefits in several blocks, is described in detail. The SoC was fabricated in a 0.18-mum 1.8-V CMOS technology and requires a total area of 72mm2 consuming 532 mW at the maximum data rates. The application-specific integrated circuit was used in lab testing where a gain of up to 9 dB was observed for the dual-antenna receiver, which demonstrates the tremendous improvement provided by spatial diversity. The results presented in this paper provide a base architecture and a performance benchmark for commercial implementations of WCDMA mobile terminals

Active constellation modification techniques for OFDM PAR reduction

OFDM is a widely adopted modulation technique for wireless communication. However, the OFDM waveform still suffers from a large peak-to-average power ratio (PAR). Larger PAR leads to higher transmit power inefficiency. In this paper, we compare two constellation modification techniques, constellation distortion (CD) and active constellation extension (ACE), to reduce the PAR of the OFDM waveform. Both techniques are similar, in the sense that the constellation symbols are modified to reduce PAR. In CD, the tradeoff is between PAR reduction and added distortion, which results in a larger bit error rate (BER). In ACE, the tradeoff is between added power and PAR reduction. A metric called normalized total power (NTP) is introduced to facilitate a comparison between these two different techniques. Using this metric, we compare the performance of the two techniques using an 802.11a OFDM waveform. We present comparisons, via simulation, in both coded and uncoded cases. The simulation results show that, for an uncoded OFDM system, ACE performs better than CD for all constellations except QPSK. However, CD is preferred over ACE when coding is present. NTP improvements using CD can be up to 4.1dB in the case of coded QPSK and up to 0.8 dB using ACE for uncoded QPSK.

Real-Time Hardware/Software Approach to Phase Noise Emulation

Phase noise is a complex and ubiquitous source of BER degradation for all communication systems. Tight interaction between the phase noise and implementation of receiver tracking loops limits the fidelity of analytical derivations. The long timescales associated with phase noise make software simulations extremely time consuming. Both of these difficulties are exacerbated in systems that employ forward error correction. This paper reports on the development of a hardware-assisted phase noise emulator. This emulator allows injection of wideband, completely programmable phase noise into a real-time system. The phase noise samples are computed entirely in software and then passed to a hardware engine. The hardware engine digitizes a low-IF signal, combines it with the computed phase noise, and re-generates an analog low-IF output. The system described in this paper supports signals up to 30 MHz wide, centered at a 70 MHz IF. The phase noise characteristics can be modeled accurately up to 10 MHz using a simple model and up to 1 MHz for a more complex model.

Diversity processing WCDMA cell searcher implementation

In this paper algorithmic and implementation innovations for a novel diversity processing based WCDMA synchronization system are presented. The system employs a dual antenna front end system and a three stage pipelined synchronization technique to achieve slot, frame and code synchronization. The slot boundary section employs a hybrid matched filter/correlator approach for maximum flexibility and to minimize power consumption. The secondary stage section employs a novel maximum likelihood algorithm to perform frame boundary identification, while the third and final stage shares the RAKE engine correlators to perform code identification. The system was implemented in a 0.18 /spl mu/m CMOS process with 1 poly and 6 metal layers. The total standard cell count is 28k implemented in 1mm/sup 2/. The average power consumed over a full frame is 2 mW from a 1.8 V supply.

Word-serial Architectures for Filtering and Variable Rate Decimation

A new flexible architecture is proposed for word-serial filtering and variable rate decimation/interpolation. The architecture is targeted for low power applications requiring medium to low data rate and is ideally suited for implementation on either an ASIC or an FPGA. It combines the small size and low power of an ASIC with the programmability and flexibility of a DSP. An efficient memory addressing scheme eliminates the need for power hungry shift registers and allows full reconfiguration. The decimation ratio, filter length and filter coefficients can all be changed in real time. The architecture takes advantage of coefficient symmetries in linear phase filters and in polyphase components.

Standardization efforts for software-defined radio

Software-defined radios (SDRs) allow the user or operator to switch between multiple waveforms without any changes to the underlying radio hardware. Minimally configurable radios that support only a few waveforms are easily managed using proprietary interfaces. However, true software radios allow thousands of different waveforms, making their configuration a nontrivial task. The level of complexity introduced by SDR has been recognized for over a decade. This paper provides an overview of different efforts to standardize the configuration and operation of SDRs. I discuss the Joint Tactical Radio Systems (JTRS) standard developed by the U.S. Army, based on the Software Communications Architecture (SCA) framework. JTRS is compared to the NASA proposal known as STRS. Both of these standards deal with higher network layers and treat the physical layer as a ‘black box.’ A new standard to describe the physical layer, SDRPHY, is discussed in detail. Finally, a few hardware-specific standardization efforts are discussed. 1 2

An EMWIN and LRIT software receiver using GNU radio

The current generation of Emergency Managers Weather Information Network (EMWIN) and Low-Rate Information Transmission (LRIT) receivers are predominantly software based and require low retail cost [1, 2]. In the Geostationary Operational Environmental Satellite R-series (GOES-R) paradigm [3], the rates for EMWIN and LRIT will be increased significantly. This paper demonstrates the feasibility of a low-cost software-based terminal, that can be used to receive GOES-R generation LRIT and EMWIN transmissions, as well as legacy EMWIN and LRIT signals. This work also describes the software architecture used to build the proposed software radio, which was designed using an advanced application programming interface (API) called GNU Radio and is designed to utilize multiple core processors on a desktop workstation [4]. We discuss the hardware requirements needed to demodulate LRIT and EMWIN signals, and summarize key system capabilities and performance.

Adaptive Automatic Gain Control for Nonlinearly, Distorted Constellations

Automatic gain control (AGC) is a key part of any demodulator that supports multilevel linear constellations. The AGC scales the received signal such that the constellation points line up with the nominal mapping. The scaling is adjusted to minimize the average distance between the received constellation point and its hard-decision equivalent. This approach has been shown to be optimal for undistorted constellations. However, it is not optimal for constellations distorted by a nonlinear amplifier. This paper investigates the relationship between AGC scaling and nonlinear distortion for coded and uncoded communications links. We present both simulation and experimental results that demonstrate significant improvement in the bit error rate (BER) by changing the AGC adaptation algorithm. The decision directed AGC algorithm is augmented with a least-mean-square (LMS) algorithm to compensate for the nonlinear distortion. This simple change can be implemented on legacy receivers with negligible increase in computational complexity.