Ahmed M. Eltawil

Optimizations of a MIMO Relay Network

Relay networks have received considerable attention recently, especially when limited size and power resources impose constraints on the number of antennas within a wireless sensor network. In this context, signal processing techniques play a fundamental role, and optimality within a given relay architecture can be achieved under several design criteria. In this paper, we extend recent optimal minimum-mean-square-error (MMSE) and signal-to-noise ratio (SNR) designs of relay networks to the corresponding multiple-input-multiple-output (MIMO) scenarios, whereby the source, relays and destination comprise multiple antennas. We investigate maximum SNR solutions subject to power constraints and zero-forcing (ZF) criteria, as well as approximate MMSE equalizers with specified target SNR and power constraint at the receiver. We also maximize the transmission rate between the source and destination subject to power constraint at the receiver.

All-Digital Self-Interference Cancellation Technique for Full-Duplex Systems

Full-duplex systems are expected to double the spectral efficiency compared to conventional half-duplex systems if the self-interference signal can be significantly mitigated. Digital cancellation is one of the lowest complexity self-interference cancellation techniques in full-duplex systems. However, its mitigation capability is very limited, mainly due to transmitter and receiver circuits impairments (e.g., phase noise, nonlinear distortion, and quantization noise). In this paper, we propose a novel digital self-interference cancellation technique for full-duplex systems. The proposed technique is shown to significantly mitigate the self-interference signal as well as the associated transmitter and receiver impairments, more specifically, transceiver nonlinearities and phase noise. In the proposed technique, an auxiliary receiver chain is used to obtain a digital-domain copy of the transmitted Radio Frequency (RF) self-interference signal. The self-interference copy is then used in the digital-domain to cancel out both the self-interference signal and the associated transmitter impairments. Furthermore, to alleviate the receiver phase noise effect, a common oscillator is shared between the auxiliary and ordinary receiver chains. A thorough analytical and numerical analysis for the effect of the transmitter and receiver impairments on the cancellation capability of the proposed technique is presented. Finally, the overall performance is numerically investigated showing that using the proposed technique, the self-interference signal could be mitigated to ~3 dB higher than the receiver noise floor, which results in up to 76% rate improvement compared to conventional half-duplex systems at 20 dBm transmit power values.

Rate Gain Region and Design Tradeoffs for Full-Duplex Wireless Communications

In this paper, we analytically study the regime in which practical full-duplex systems can achieve larger rates than an equivalent half-duplex systems. The key challenge in practical full-duplex systems is uncancelled self-interference signal, which is caused by a combination of hardware and implementation imperfections. Thus, we first present a signal model which captures the effect of significant impairments such as oscillator phase noise, low-noise amplifier noise figure, mixer noise, and analog-to-digital converter quantization noise. Using the detailed signal model, we study the rate gain region, which is defined as the region of received signal-of-interest strength where full-duplex systems outperform half-duplex systems in terms of achievable rate. The rate gain region is derived as a piecewise linear approximation in log-domain, and numerical results show that the approximation closely matches the exact region. Our analysis shows that when phase noise dominates mixer and quantization noise, full-duplex systems can use either active analog cancellation or baseband digital cancellation to achieve near-identical rate gain regions. Finally, as a design example, we numerically investigate the full-duplex system performance and rate gain region in typical indoor environments for practical wireless applications.

Self-interference cancellation with nonlinear distortion suppression for full-duplex systems

In full-duplex systems, due to the strong self-interference signal, system nonlinearities become a significant limiting factor that bounds the possible cancellable self-interference power. In this paper, a self-interference cancellation scheme for full-duplex orthogonal frequency division multiplexing systems is proposed. The proposed scheme increases the amount of cancellable self-interference power by suppressing the distortion caused by the transmitter and receiver nonlinearities. An iterative technique is used to jointly estimate the self-interference channel and the nonlinearity coefficients required to suppress the distortion signal. The performance is numerically investigated showing that the proposed scheme achieves a performance that is less than 0.5dB off the performance of a linear full-duplex system.

Design and Implementation of a Sort-Free K-Best Sphere Decoder

This paper describes the design and very-large-scale integration (VLSI) architecture for a 4 × 4 breadth-first K-best multiple-input-multiple-output (MIMO) decoder using a 64 quadrature-amplitude modulation (QAM) scheme. A novel sort-free approach to path extension, as well as quantized metrics result in a high-throughput VLSI architecture with lower power and area consumption compared to state-of-the-art published systems. Functionality is confirmed via a field-programmable gate array (FPGA) implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given, and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized application-specific IC (ASIC) implementation in a 65-nm CMOS technology.

A Radius Adaptive K-Best Decoder With Early Termination: Algorithm and VLSI Architecture

This paper presents a novel algorithm and architecture for K-Best decoding that combines the benefits of radius shrinking commonly associated with sphere decoding and the architectural benefits associated with K-Best decoding approaches. The proposed algorithm requires much smaller K and possesses the advantages of branch pruning and adaptively updated pruning threshold while still achieving near-optimum performance. The algorithm examines a much smaller subset of points as compared to the K-Best decoder. The VLSI architecture of the decoder is based on a pipelined sorter-free scheme. The proposed K-Best decoder is designed to support a 4 × 4 64-QAM system and is synthesized with 65-nm technology at 158-MHz clock frequency and 1-V supply. The synthesized decoder can support a throughput of 285.8 Mb/s at 25-dB signal-to-noise ratio with an area of 210 kGE at 12.8-mW power consumption.

Memristor Multiport Readout: A Closed-Form Solution for Sneak Paths

In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements. The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings. The new method requires fewer reading steps compared to previously reported techniques, and has a very small impact on the memory density. To verify the underlying theory, the proposed system is simulated using Synopsys HSPICE showing the ability to achieve a 100% sneak-path error-free memory. In addition, the effect of quantization bits on the system performance is studied.

Cross Layer Error Exploitation for Aggressive Voltage Scaling

This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3 GPP WCDMA modem

Design and Implementation of a Scalable Channel Emulator for Wideband MIMO Systems

Wireless channel emulation is becoming increasingly important, particularly with the advent of multiple-input-multiple-output (MIMO) systems, where system performance is highly dependent on the accurate representation of the channel condition. In this paper, we compare the conventional finite impulse response (FIR)-based emulator versus solely performing the emulation in the frequency domain. We show that for single-input-single-output (SISO) systems, FIR-based emulators are computationally efficient but that the complexity rapidly becomes impractical for larger array sizes. On the other hand, frequency-domain approaches exhibit a fixed initial complexity cost that grows at a reduced rate as a function of the array size, resulting in significant savings in complexity for higher order arrays. As an illustrative example of this approach, field-programmable gate array (FPGA) architecture implementing a sample 3 times 3 MIMO system exhibits resource savings of up to 67% over a similarly constrained FIR approach. The architecture is discussed in detail, and implementation results, as well as laboratory measurements, are presented.

Linear Decentralized Estimation of Correlated Data for Power-Constrained Wireless Sensor Networks

In this paper, we consider distributed estimation of an unknown random vector by using wireless sensors and a fusion center (FC). We adopt a linear model for distributed estimation of a vector source where both observation models and sensor operations are linear and the multiple access channel (MAC) is coherent. Two cases are considered: Noiseless fusion center and Noisy fusion center. In the case of a Noiseless fusion center (where there is no noise at the fusion center), the sensor precoders are designed to minimize the mean square error (MSE) at the fusion center. A closed form solution is found and it is shown that the system performance approaches the benchmark as long as the number of messages transmitted by each sensor is equal to the length of the vector source. Subsequently, if there is noise at the fusion center and one is interested in a closed form solution, a filter is designed to cancel out the effect of noise at the fusion center. This separate design will come at the expense of losing performance. An alternative iterative solution can be found when considering noise at the fusion center where sensor precoders are designed to minimize the MSE at the fusion center subject to transmit power constraints at each sensor. It is shown that the proposed scheme always converges. Finally, simulations are provided to verify the analysis and present the performance of the proposed schemes.