Eugene M. Chow

Novel packaging with rematable spring interconnect chips for MCM

A novel packaging approach has been demonstrated for circuits connected with flexible microsprings. The approach is based on silicon micromachined features and results in a highly accurate and low cost packaging solution. The micromachined features were processed into silicon with an anisotropic wet etch forming inverted pyramidal micro-pits. The pits are integrated into the chips along with arrays of flexible and compliant interconnects arranged in a daisy chain arrays on 180 µm pitch. Packages based on two chips with matching set of pits have been assembled and characterized. First level reliability tests have been performed in 0°C–100°C temperature cycling, 85/85 temperature humidity bias and high-current soak. Multiple “remating”; tests were also carried out as the packages were taken apart and reassembled together. The “pit and spring” integration is expected to equally address not only the performance and functionality of the completed package but also its reliability and cost.

Pressure Contact Micro-Springs in Small Pitch Flip-Chip Packages

This work investigates electrical pressure contacts based on a micro-spring with orders of magnitude smaller pitch and force than conventional pressure contacts. The springs are beams which curl out of the surface and can be used for wafer-scale testing and packaging. They are fabricated with standard wafer-scale thin film techniques and have been previously demonstrated on active silicon integrated circuits. Single springs and their electrical contacts are characterized with force versus compression and compression versus resistance measurements. Flip-chip packages with hundreds of micro-springs were assembled with 20-mum pad pitch and 40-mum spring pitch. Each spring operates with a force of approximately 0.01 g and contacts a gold pad. These packages are shown to have stable resistance values during both in-situ thermocycle (0degC to 125degC) and humidity testing (60degC at 95%RH). Spring electrical contacts inside the package are shown not to degrade during environmental testing through measurements of four-wire resistance and electrical isolation structures. High-speed glitch measurements are performed to confirm that the pressure contact does not have intermittent opens during thermocycling. These results suggest that a low-force solder-free pressure spring contact is a viable technology for next generation flip-chip packaging

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm times 6.5 mm with 48 spring contacts on a 0.8 mm times 0.65 mm grid array, each spring measuring 400 mum times 100 mum. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20 000 hot plate thermal cycles and >1000 oven thermal cycles without failure.

Solder-Free Pressure Contact Micro-Springs in High-Density Flip-Chip Packages

This work investigates electrical pressure contacts based on a micro-spring with orders of magnitude smaller pitch and force than conventional pressure contacts. Flip-chip packages were assembled with hundreds of micro-springs at 20 mum pad-pitch, 40 mum spring-pitch, and an operating force of 0.01 gram on gold pads. These packages are shown to have stable resistance values during both in-situ thermocycle (0 degC to 125 degC) and humidity testing (60 degC at 95% RH). High-speed glitch measurements are performed to confirm the pressure contact does not have intermittent opens during thermocycling. These results suggest that a low-force solder-free pressure spring contact is a viable technology for next generation flip-chip packaging

Fine-feature patterning of self-aligned polymeric thin-film transistors fabricated by digital lithography and electroplating

Spatially controlled jet-printed etch masks, having a minimum drop size of 40–50μm, were used to define gap patterns having a minimum feature size of ∼10μm. The defined gaps, in combination with nickel electroplating, were used to create bottom-gate electrode thin-film transistors (TFTs) with gate lengths of 10–20μm and gate widths of 150μm. Self-aligned source/drain top contacts were used for fabricating polythiophene-based TFT devices having channel width-to-length ratios of ∼4. A typical p-channel TFT device had an on/off ratio of 107, threshold voltage of −1V, and field-effect mobility of 0.034cm2∕Vs.

Micro-spring force characterization and applications in integrated circuit packaging and scanning probe MEMS metrology

Micro-springs are characterized and demonstrated in integrated circuit (IC) packaging and microelectromechanical system (MEMS) metrology applications. The springs are based on lithographically defined stress-engineered films and are compliant, electrically conducting and have micrometer scale dimensions. The force-displacement is experimentally measured and found to have constant stiffness through the majority of compression. Fretting experiments are performed to investigate the potential for intermittent electrical contact when the springs are used as a solder-less pressure contact for integrated circuit packaging. While operating at <1 mN of force, orders of magnitude lower than macroscopic connectors, no glitches slower than 4 nsec are observed for thousands of shake cycles. The springs are also demonstrated as scanning probes for non-destructive imaging of high-aspect ratio MEMS structures. Sidewall line-scans and tapping mode images in deep silicon trenches are presented using tip heights over ten times taller than commercial probes.

A package demonstration with solder free compliant flexible interconnects

Flexible, stress-engineered spring interconnects are a novel technology potentially enabling room temperature assembly approaches to building highly integrated and multi-chip modules (MCMs). Such interconnects are an essential solder-free technology facilitating the MCM package diagnostics and rework. Previously, we demonstrated the performance, functionality, and reliability of compliant micro-spring interconnects under temperature cycling, humidity bias and high-current soak. Currently, we demonstrate for the first time the package with the 1st level conventional fine pitch C4 solder bump interconnects replaced by the arrays of microsprings. Dedicated CMOS integrated circuits (ICs) have been assembled onto substrates using these integrated microsprings. Metrology modules on the ICs are designed and used to characterize the connectivity and resistance of each microspring site.

Open and closed loop manipulation of charged microchiplets in an electric field

We demonstrate the ability to orient, position, and transport microchips (“chiplets”) with electric fields. In an open-loop approach, modified four phase traveling wave potential patterns manipulate chiplets in a dielectric solution using dynamic template agitation techniques. Repeatable parallel assembly of chiplets is demonstrated to a positional accuracy of 6.5 μm using electrodes of 200 μm pitch. Chiplets with dipole surface charge patterns are used to show that orientation can be controlled by adding unique charge patterns on the chiplets. Chip path routing is also demonstrated. With a closed-loop control system approach using video feedback, dielectric, and electrophoretic forces are used to achieve positioning accuracy of better than 1 μm with 1 mm pitch driving electrodes. These chip assembly techniques have the potential to enable future printer systems where inputs are electronic chiplets and the output is a functional electronic system.

Package demonstration of an interposer with integrated TSVs and flexible compliant interconnects

We report on the development of a test package that utilizes a passive silicon interposer with high density and high aspect ratio TSVs, each integrated with compliant flexible interconnect on one side of the interposer. As opposed to conventional approaches, where TSV interposers are populated with C4 and/or fine pitch micro bumps with multiple interfaces to reflow and permanently attach, our TSV interposers are integrated with micro-spring interconnects on a single side or, potentially, on both sides to provide a truly reworkable or reusable (“rematable”) MCM platform. This makes it possible to test die in package while retaining the ability to replace any that are found flawed. This is a key requirement for increasing assembly yield of advanced MCM packages.

Micro chiplet printer for micro-scale photovoltaic system assembly

The micro-CPV concept uses an array of micro unit cells (or elements) such that the material usage, weight, and the required structural strength can all be scaled down favorably. Unfortunately, one of the essential unfavorable scaling factors is the assembly cost due to the many micro scale components that must be deposited, positioned, oriented, and connected over large areas. By using a dynamic electric field template, we successfully demonstrate chiplet printing - assembling a desired solar cell chip at a designated location with well controlled orientation. Xerographic printing systems utilizing this method can be extended to provide high-throughput, on-demand heterogeneous assembly of micro-CPV systems.