Evangelos Vassalos

RNS assisted image filtering and edge detection

Image edge detection plays a fundamental role in image processing as well as in computer and machine vision while when applied in medical images can improve medical diagnosis. Thus, efficient hardware implementation of an edge detection system is highly appreciated. In this work we propose a novel architecture for image filtering and edge detection using the Residue Number System (RNS). A VLSI implementation of the proposed architecture dictates that the employment of RNS for the arithmetic processing leads to small hardware complexity and high operation frequency.

On the Design of Modulo 2 n ±1 Subtractors and Adders/Subtractors

Novel architectures for designing modulo 2n+1 subtractors and combined adders/subtractors are proposed in this manuscript. Both the normal and the diminished-one representations of the operands are considered. Unit gate estimates and CMOS VLSI implementations reveal that the proposed modulo 2n+1 subtractors for operands in the normal representation are more efficient than those previously proposed. The proposed diminished-one modulo 2n+1 subtractors have a complexity similar to that of the corresponding diminished-one adders. Modulo 2n−1 subtractors and adders/subtractors are also considered for the sake of completeness and a comparison between alternative architectures is provided.

CSD-RNS-based Single Constant Multipliers

Architectures for designing single constant multipliers in Residue Number System (RNS) for moduli of the 2n−1, 2n and 2n + 1 forms are introduced with the constant operand being recoded in Signed-Digit representation. Two methodologies are proposed. In the first one a straightforward implementation of the shift-and-add algorithm is adopted, while in the second one a graph-based approach is used. Both methodologies result in circuits that are shown to be efficient in terms of area and delay.

Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion

The diminished-one representation has been proposed for RNS-based systems with moduli of the 2^n+1 forms as an encoding that is more efficient than the normal representation in the arithmetic processing units. However, its use necessitates a two-step reverse conversion, in which a diminished-to-normal conversion is first performed before the final residue-to-binary conversion resulting in performance loss. In this paper we introduce efficient modulo 2^n+1 adders, sub tractors and multipliers that accept diminished-one operands at their inputs and derive normal operands at their outputs, that is, we embed the diminished-to-normal conversion within the arithmetic processing. Experimental results show that the proposed one-step approach is more efficient in terms of delay.

Reverse converters for RNSs with diminished-one encoded channels

The diminished-one encoding is often considered when representing the operands in the modulo 2k+1 channels of a Residue Number System (RNS) since it can offer increased arithmetic processing speed. However, limited research is available on the design of residue-to-binary (reverse) converters for RNSs that use the diminished-one encoding in one or more channels. In this paper we introduce a simple methodology for designing such converters which can be applied to reverse converters based on the Chinese Remainder Theorem (CRT) or the New CRT-I method. Efficient converters for three moduli sets, covering different dynamic ranges, are also analytically presented. The proposed converters are shown to be area, delay and power efficient for several moduli sets.

Combined SD-RNS Constant Multiplication

In this paper we present constant multiplication architectures for the Residue Number System (RNS) moduli set {2 n -1, 2 n , 2 n +1} using the Signed-Digit (SD) representation for recoding the constant operand. The resulting circuits require a small number of partial products, hence, their area and delay is also small. Keywords-Residue number system, modulo {2 n -1, 2 n , 2 n +1} arithmetic, constant multiplication, signed-digit number system, CSD representation.

Modulo 2 n −2 arithmetic units

A modulo 2n-2 value has been proposed in Residue Number System (RNS)-based systems for the design of FIR filters and communication components. However, all modulo 2n-2 arithmetic units that were used have been based either on look-up tables or on generic modulo arithmetic structures. In this work we propose novel modulo 2n-2 adder, multiplier as well as residue generation architectures that take advantage of the inherent properties of modulo 2n-2 arithmetic. The proposed circuits are based on corresponding circuits for modulo 2n-1-1 arithmetic and some simple logic resulting that way to efficient implementations regarding the area, delay and average power dissipation. The evaluation and experimental results of the proposed circuits confirm their efficiency.

SUT-RNS Forward and Reverse Converters

Stored Unibit Transfer (SUT) has been recently proposed as a redundant high-radix encoding for the channels of a Residue Number System (RNS) that can improve the efficiency of conventional redundant RNS. In this paper we propose modulo 2^n±1 forward and reverse converters for the SUT-RNS encoding. The proposed converters are based on parallel-prefix binary or modulo adders and are therefore very efficient.

Novel modulo 2 n +1 subtractors

Novel architectures for designing modulo 2n+1 subtractors are introduced, for both the normal and the diminished-one number representation of the operands. Zero-handling is also considered in the diminished-one operand representation case. The modulo 2n+1 subtractors for operands in the normal representation that are proposed are shown to be more efficient in area, delay and power dissipation than the currently most efficient ones. The proposed diminished-one modulo 2n+1 subtractors offer similar characteristics to those of the corresponding diminished-one adders.

Efficient architectures for modulo 2n − 2 arithmetic units

Moduli of the 2n and 2n ± 1 forms are usually employed in designs that adopt the residue number system. However, in several cases such as in finite impulse response filters and communication components, a modulo value equal to 2n − 2 can be used. So far, modulo 2n − 2 arithmetic units have been based either on look-up tables or on generic modulo arithmetic units. In this work, by taking advantage of the properties of modulo 2n − 2 arithmetic, we propose efficient modulo 2n − 2 multi-operand adder, multiplier as well as squarer architectures. The proposed circuits are based on the corresponding ones for modulo 2n−1 − 1 arithmetic and some simple logic. Experimental results validate that the proposed circuits achieve significant area and delay savings compared to those previously presented.