Dimitris Bakalis

An efficient seeds selection method for LFSR-based test-per-clock BIST

Built-in self-test (BIST) is an effective approach for testing large and complex circuits. When BIST is used, a test pattern generator (TPG), a test response verifier and a BIST controller accompany the circuit under test (CUT) in the chip, creating a self-testable circuit. In this paper we propose a new algorithm for seeds selection in LFSR (linear feedback shift register) based test-per-clock BIST. The proposed algorithm uses the well-known concept of solving systems of linear equations and, based on heuristics, minimizes the number of seeds and test vectors while achieving 100% fault coverage. Experimental results indicate that it compares favorably to the other known techniques.

Efficient partial scan cell gating for low-power scan-based testing

Gating of the outputs of a portion of the scan cells (partial gating) has been recently proposed as a method for reducing the dynamic power dissipation during scan-based testing. We present a new systematic method for selecting, under area and performance design constraints, the most suitable for gating subset of scan cells as well as the proper gating value for each one of them, aiming at the reduction of the average switching activity during testing. We show that the proposed method outperforms the corresponding already known methods, with respect to average dynamic power dissipation reduction.

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.

Scan cell ordering for low power BIST

Power dissipation during scan-based testing has gained significant importance in the past few years. In this work we examine the use of transition frequency based on scan cell ordering techniques in pseudorandom scan based BIST in order to reduce average power dissipation. We also propose the resetting of the input register of the circuit together with ordering of its elements to further reduce average power dissipation. Experimental results indicate that the proposed techniques can reduce average power dissipation up to 57.7%.

ON IMPLEMENTING EFFICIENT MODULO 2n + 1 ARITHMETIC COMPONENTS

It is shown that a diminished-1 adder, with minor modifications, can be also used for the modulo 2n + 1 addition of two n-bit operands in the weighted representation, if the sum of its input operands is decreased by one. This modified diminished-1 adder can perform n-bit modulo 2n + 1 addition in less area and time than solutions that are based on the use of binary adders and/or weighted modulo 2n + 1 adders. Therefore, it can be applied effectively to all weighted modulo 2n + 1 arithmetic components that finally derive two n-bit addends. A small number of weighted arithmetic components have in the past adopted such a scheme without presenting this general theory. By applying this idea, we propose novel multi-operand modulo 2n + 1 adders (MOMAs) and residue generators (RGs). Experimental results indicate that the resulting arithmetic components offer significant savings in delay, implementation area and average power consumption compared to the currently most efficient solutions.

Fast modulo 2n+1 multi-operand adders and residue generators

In this manuscript novel architectures for modulo 2^n+1 multi-operand addition and residue generation are introduced. The proposed arithmetic components consist of a translation stage, an inverted end-around-carry carry-save-adder tree and an enhanced diminished-1 modulo 2^n+1 adder. Qualitative and quantitative results indicate that the proposed architectures result in significantly faster and in several cases smaller circuits than the previously proposed.

On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components

The contribution of this paper is twofold. We firstly show that an augmented diminished-1 adder can be used for the modulo 2n +1 addition of two n-bit operands in the weighted representation, if it is driven by operands whose sum has been decreased by 1. This scheme outperforms solutions that are based on the use of binary adders and/or weighted modulo 2n + 1 adders in both area and delay terms. We then apply this scheme in the design of residue generators (RGs) and multi-operand modulo adders (MOMAs). The resulting arithmetic components remove at least a whole parallel adder out of the critical path of the currently most efficient proposals. Experimental results indicate savings of more than 30% in execution time and of approximately 19% in implementation area when the proposed architectures are used.

Efficient modulo 2 n ±1 squarers

Modulo 2^n+/-1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic algorithms. In this paper we propose, in a unified way, architectures for their design that are based on the radix-4 modified Booth encoding. For the modulo 2^n+1 case, both the normal and the diminished-one representations are considered. Experimental results show that the proposed squarers offer significant savings in the implementation area over previous proposals that can reach up to 38% for sufficiently large operand widths, while in many cases a small improvement in execution delay can also be achieved.

On the design of self-testing checkers for modified Berger codes

One of several approaches for designing highly-reliable systems relies on using error detecting codes (EDCs) and implementing digital circuits as self-checking. One class of EDCs that has been very often used to implement self-checking circuits are Berger codes. Although several self-testing checkers (STCs) for Berger codes have been proposed in the past, they mostly present area and delay results based on gate counts and gate levels and not on real implementations. In this work we consider real implementations and present and evaluate the area, delay and power characteristics of STCs for modified Berger codes that are based on: (a) parallel counters and (b) sorting networks. Preliminary results indicate that STCs based on parallel counters are smaller and consume less power than the STCs based on sorting networks.

Low power BIST for Wallace tree-based multipliers

The low power as a feature of a BIST scheme is a significant target due to quality as well as cost related issues. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power Built In Self Test (BIST) scheme for them. We propose several design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BIST scheme for the derived multipliers is achieved by: (a) introducing suitable Test Pattern Generators (TPG); (b) properly assigning the TPG outputs to the multiplier inputs; and (c) significantly reducing the test set length with respect to earlier schemes; Our results indicate that the total power dissipated during test can be reduced from 64.8% to 72.8%, while the average power per test vector can be reduced from 19.6% to 27.4% and the peak power dissipation can be reduced from 16.8% to 36.0%, depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST scheme implementation area is small.