Ezra Bussmann

Dynamics of solid thin-film dewetting in the silicon-on-insulator system

Using low-energy electron microscopy movies, we have measured the dewetting dynamics of single-crystal Si(001) thin films on SiO2 substrates. During annealing (T>700 °C), voids open in the Si, exposing the oxide. The voids grow, evolving Si fingers that subsequently break apart into self-organized three-dimensional (3D) Si nanocrystals. A kinetic Monte Carlo model incorporating surface and interfacial free energies reproduces all the salient features of the morphological evolution. The dewetting dynamics is described using an analytic surface-diffusion-based model. We demonstrate quantitatively that Si dewetting from SiO2 is mediated by surface-diffusion driven by surface free-energy minimization.

Probing the limits of Si:P δ-doped devices patterned by a scanning tunneling microscope in a field-emission mode

Recently, a single atom transistor was deterministically fabricated using phosphorus in Si by H-desorption lithography with a scanning tunneling microscope (STM). This milestone in precision, achieved by operating the STM in the conventional tunneling mode, typically utilizes slow ( ∼102 nm2/s) patterning speeds. By contrast, using the STM in a high-voltage (>10 V) field-emission mode, patterning speeds can be increased by orders of magnitude to ≳104 nm2/s. We show that the rapid patterning negligibly affects the functionality of relatively large micron-sized features, which act as contacting pads for these devices. For nanoscale structures, we show that the resulting electrical transport is consistent with the donor incorporation chemistry constraining the electrical dimensions to a scale of 10 nm even though the pattering spot size is 40 nm.

All-optical lithography process for contacting nanometer precision donor devices

We describe an all-optical lithography process that can make electrical contact to nanometer-precision donor devices fabricated in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.

Dual-gate operation and carrier transport in SiGe p–n junction nanowires

We investigate carrier transport in silicon-germanium nanowires with an axial p-n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carriers in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source-drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source-drain configuration, current is limited by the nickel/n-side Schottky contact.We investigate carrier transport in silicon-germanium nanowires with an axial p-n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source-drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source-drain configuration, current is limited by the nickel/n-side Schottky contact.