F. Arnaud
STMicroelectronics
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Publication
Featured researches published by F. Arnaud.
symposium on vlsi technology | 2012
N. Planes; O. Weber; V. Barral; S. Haendler; D. Noblet; D. Croain; M. Bocat; P.-O. Sassoulas; X. Federspiel; A. Cros; A. Bajolet; E. Richard; B. Dumont; P. Perreau; D. Petit; Dominique Golanski; C. Fenouillet-Beranger; N. Guillot; M. Rafik; V. Huard; S. Puget; X. Montagner; M.-A. Jaud; O. Rozeau; O. Saxod; F. Wacquant; F. Monsieur; D. Barge; L. Pinzelli; M. Mellier
For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.
IEEE Journal of Solid-state Circuits | 2014
David Jacquet; Frederic Hasbani; Philippe Flatresse; Robin Wilson; F. Arnaud; Giorgio Cesana; Thierry Di Gilio; Christophe Lecocq; Tanmoy Roy; Amit Chhabra; Chiranjeev Grover; Olivier Minez; Jacky Uginet; Guy Durieu; Cyril Adobati; Davide Casalotto; Frederic Nyer; Patrick Menut; Andreia Cathelin; Indavong Vongsavady; Philippe Magarshack
This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.
international electron devices meeting | 2004
F. Boeuf; F. Arnaud; M.T. Basso; D. Sotta; F. Wacquant; J. Rosa; N. Bicais-Lepinay; H. Bernard; J. Bustos; S. Manakli; M. Gaillardin; J. Grant; T. Skotnicki; B. Tavel; B. Duriez; M. Bidaud; P. Gouraud; C. Chaton; P. Morin; J. Todeschini; M. Jurdit; L. Pain; V. De-Jonghe; R. El-Farhane; S. Jullian
In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonstrated. GP nFET/pFET devices feature I/sub on/= 820/spl mu/A//spl mu/m/340 /spl mu/A//spl mu/m at I/sub off/ = 20nA//spl mu/m at V/sub dd/=1.0V. RO features Tp < 10ps. LP devices feature I/sub on/= 505 /spl mu/A//spl mu/m 1240 /spl mu/A//spl mu/m at I/sub off/ = 0.1 nA//spl mu/m at V/sub dd/= 1.2V. In addition, high-voltage 50A/2.5V devices are made to complete the CMOS platform.
symposium on vlsi technology | 2006
C. Ortolland; Pierre Morin; C. Chaton; E. Mastromatteo; C. Populaire; S. Orain; F. Leverd; P. Stolk; F. B¿uf; F. Arnaud
In this paper, we present an optimization path of stress memorization technique (SMT) for 45nm node and below using a nitride capping layer. We demonstrate that the understanding of coupling between nitride properties, dopant activation and poly-silicon gate mechanical stress allows enhancing nMOS performance by 7% without pMOS degradation. In contrast to previously reported works on SMT (Chen et al., 2004) - (Singh et al., 2005), a low-cost process compatible with consumer electronics requirements has been successfully developed
international electron devices meeting | 2012
F. Arnaud; N. Planes; O. Weber; V. Barral; S. Haendler; Philippe Flatresse; F. Nyer
This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (Vdd; Vbb). A simple switching energy efficiency model is then proposed allowing the (Vdd; Vbb) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of -30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.
international electron devices meeting | 2011
E.G. Ioannidis; S. Haendler; A. Bajolet; T. Pahron; N. Planes; F. Arnaud; R.A. Bianchi; M. Haond; D. Golanski; J. Rosa; C. Fenouillet-Beranger; P. Perreau; C. A. Dimitriadis; G. Ghibaudo
In this paper, we present, for the first time, a thorough investigation of low frequency noise (LFN) and statistical noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors. The experimental results are well interpreted by Monte-Carlo LFN simulations based on the random spatial and energy distribution of discrete traps in the gate dielectric. Our results clearly indicate that the LFN variability of 28nm FD-SOI CMOS technology is improved as compared to previous 45nm and 32nm bulk CMOS technologies.
symposium on vlsi technology | 2004
F. Arnaud; B. Duriez; B. Tavel; L. Pain; J. Todeschini; M. Jurdit; Y. Laplanche; F. Boeuf; F. Salvetti; D. Lenoble; J.P. Reynard; F. Wacquant; Pierre Morin; N. Emonet; D. Barge; M. Bidaud; D. Ceccarelli; P. Vannier; Y. Loquet; H. Leninger; F. Judong; C. Perrot; I. Guilmeau; R. Palla; A. Beverina; V. DeJonghe; M. Broekaart; V. Vachellerie; R.A. Bianchi; B. Borot
A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 /spl mu/m/sup 2/ bit-cells with 240mV of SNM and 35 /spl mu/A of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 /spl mu/A/ /spl mu/m and 400 /spl mu/A/ /spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/ = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. /spl mu/m) and analog voltage gain factor (G/sub m//G/sub d/>2000 for L = 10 /spl mu/m) at the leading edge for this process technology. NBTI criteria at 125/spl deg/C for both LP and GP transistors are presented and characterized at overdrive conditions.
international electron devices meeting | 2005
A. Pouydebasque; B. Dumont; S. Denorme; F. Wacquant; M. Bidaud; C. Laviron; A. Halimaoui; C. Chaton; J.D. Chapon; P. Gouraud; F. Leverd; H. Bernard; S. Warrick; D. Delille; K. Romanjek; R. Gwoziecki; N. Planes; S. Vadot; I. Pouilloux; F. Arnaud; F. Boeuf; T. Skotnicki
In this work, we report on the integration of 30nm gate length CMOS devices fabricated using laser spike annealing (LSA). Considerably improved short channel effects and drive current (+10% I<sub>on</sub> at constant I<sub>off</sub> for NMOS) are demonstrated on samples using LSA. Excellent I<sub>on</sub>I<sub>off</sub> characteristics (I<sub>on </sub> = 940 muA/mum I<sub>off</sub> = 200 muA/mum for NMOS and I<sub>on</sub> = 390muA/mum I<sub>off</sub> = 50 nA/mum for PMOS at V<sub>dd</sub> = 1 V) are measured that are at the leading edge of the state of the art. Moreover, an enhanced dynamic behavior (-6% in ring oscillator delay) and improved characteristics of high density SRAM bit-cells (+24% I<sub>cell</sub> for the same 1<sub>sb</sub>) are reported. These results demonstrate the potential of LSA in the perspective of 30 nm device integration of a 45 nm bulk CMOS platform
international electron devices meeting | 2003
B. Tavel; M. Bidaud; N. Emonet; D. Barge; N. Planes; H. Brut; D. Roy; J.C. Vildeuil; R. Difrenza; K. Rochereau; M. Denais; V. Huard; P. Llinares; S. Bruyere; C. Parthasarthy; N. Revil; R. Pantel; F. Guyader; L. Vishnubotla; K. Barla; F. Arnaud; P. Stolk; M. Woo
This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4/spl times/ reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.
european solid-state device research conference | 2014
F. Andrieu; M. Cassé; E. Baylac; P. Perreau; Olivier Nier; D. Rideau; Remy Berthelon; F. Pourchon; A. Pofelski; B. De Salvo; Claire Gallon; Vincent Mazzocchi; David Barge; C. Gaumer; Olivier Gourhant; A. Cros; Vincent Barral; R. Ranica; N. Planes; W. Schwarzenbach; E. Richard; E. Josse; O. Weber; F. Arnaud; M. Vinet; O. Faynot; M. Haond
We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.