O. Weber

28nm FDSOI technology platform for high-speed low-voltage digital applications

For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

Sources responsible for local and inter-die threshold voltage (V_t) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time. Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local V_t variability and it is found that SOI thickness (T_Si) variations have a negligible impact down to T_Si=7 nm. Moreover, T_Si scaling is shown to limit both local and inter-die V_t variability induced by gate length fluctuations. The highest matching performance ever reported for 25 nm gate length MOSFETs is achieved (A_Vt=0.95 mV.mum), demonstrating the effectiveness of the undoped ultra-thin FDSOI architecture in terms of V_t variability control.

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

Electron and hole mobility in HfO/sub 2//metal gate MOSFETs is deeply studied through low-temperature measurements down to 4.2 K. Original technological splits allow the decorrelation of the different scattering mechanisms. It is found that even when charge trapping is negligible, strong remote coulomb scattering (RCS) due to fixed charges or dipoles causes most of the mobility degradation. The effective charges are found to be located in the HfO/sub 2/ near the SiO/sub 2/ interface within 2 nm. Experimental results are well reproduced by RCS calculation using 7/spl times/10/sup 13/ cm/sup -2/ fixed charges at the HfO/sub 2//SiO/sub 2/ interface. We also discuss the role of remote phonon scattering in such gate stacks. Interactions with surface soft-optical phonon of HfO/sub 2/ are clearly evidenced for a metal gate but remain of second order. All these remote interactions are significant for an interfacial oxide thickness up to 2 nm, over which, these are negligible. Finally, the metal gate (TiN) itself induces a modified surface-roughness term that impacts the low to high effective field mobility even for the SiO/sub 2/ gate dielectric references.

Advances, challenges and opportunities in 3D CMOS sequential integration

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V<inf>T</inf>-variability performances are obtained (A<inf>VT</inf>=1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V<inf>DD</inf>=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ<inf>SNM</inf><SNM/6) down to V<inf>DD</inf>=0.7V. We also demonstrate ultra-low leakage (<0.5pA/µm) on UT2B devices at L<inf>G</inf>= 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

Strained tunnel FETs with record I ON : first demonstration of ETSOI TFETs with SiGe channel and RSD

We present for the first time Tunnel FETs obtained with a FDSOI CMOS process flow featuring High-K Metal Gate, ultrathin body compressively strained Si_1-xGe_x (x from 0 to 30%) based channels, and Si_0.7Ge_0.3 Raised SD. We analyse the tunnelling improvements due to the different technological injection boosters: ultrathin body & EOT, strain, low band gap source, and low temperature SD anneal. For the first time, TFETs with large ON current (up to 428μA/μm) are demonstrated (with >;x1000 I_ON gain vs. SOI).

Engineered substrates for future More Moore and More than Moore integrated devices

In 1991, M. Bruel (1) invented and patented the Smart Cut technology to fabricate Silicon On Insulator (SOI) substrates. The process relies on the transfer of a high quality single crystal layer from one wafer to another: implantation of gaseous ions in a single crystal wafer, direct bonding on a stiffener and splitting (Fig 1). The invention of this SOI process combined with the entrepreneurship of SOITEC paved the way to high quality SOI substrates mass production. Today, SOI is a mature product (up to 300mm diameter) and now developments are focused on the integration of new materials and functionalities in order to improve device performances and enlarge the application spectrum.

Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

We report a detailed comparison of low and high-Vd transport between various substrate- and process-induced strained MOSFETs down to 40nm gate lengths. Thanks to an original extraction method and low temperature measurements, we demonstrate that the mobility behaviour is deeply impacted by the down-scaling because of Coulomb scattering. Introducing this behaviour into a saturation current model, we clearly explain the I/sub ON/ enhancement trend of all strained devices.

14nm FDSOI technology for high speed and energy efficient applications

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m2 high-density bitcell and two 0.090°m2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.