F.C. Castaldo

Magnetically Coupled Current Sensors Using CMOS Split-Drain Transistors

Integrated current-sensing circuits intended for smart-power and embedded applications featuring galvanic isolation are implemented. They are based on magnetic detection using a CMOS-compatible split-drain transistor that provides a very linear output current versus magnetic field. Two approaches are used to generate the magnetic field: the coil approach and the strip approach. In the first, the current to be sensed flows through an integrated coil placed atop the split-drain transistor and produces a magnetic coupling strong enough to cause a detectable current. The second approach features an array of 126 paralleled split-drain transistors placed along a metal strip intended to carry higher current levels. Both techniques were realized as integrated current sensors built in 0.35 mum CMOS technology. The calculated and measured sensitivities were around 1 and 0.75 muA/A for the coil and strip approaches, respectively. For a typical single split-drain bias current of 50 muA, the minimum detectable currents within 1 Hz are 2.8 and 42 muA/radicHz for the coil and strip approaches, respectively. The strip can carry currents up to 500 mA, whereas the flowing current in the coil is limited to 20 mA. Thus, the choice is based on the resolution and sensing current level of the application.

Magnetically-coupled current sensors using CMOS split-drain transistors

Integrated current sensing circuits intended for Smart-Power and embedded applications featuring galvanic isolation are implemented. They are based on magnetic detection using the CMOS compatible split-drain transistor (MAGFET) that provides a very linear output current versus magnetic field. Two approaches are used to generate the magnetic field. The Coil approach and the Strip approach. In the first one the current to be sensed flows through an integrated coil placed atop the split-drain transistor and produces a relatively strong magnetic coupling enough to cause a detectable current. The second approach features an array of 126-paralleled split-drain transistors along a metal strip intended to carry higher current levels. Both techniques were realized as integrated current sensors built in 0.35 mum CMOS technology. The calculated and measured sensitivities were around 1 muA/A and 0.75muA/radicA for the Coil and Strip approaches respectively. For a typical single split-drain bias current of 50 muA, the minimum detectable current within 1Hz are 2.8 muA/radicHz and 42 muA/radicHz for the Coil and Strip approaches respectively. The Strip can carry currents up to 500 mA, whereas the flowing current in the Coil is limited to 20 mA. Thus, the choice is based on the resolution and sensing current level of the application.

Shunt-Zero Based on CMOS Split-Drain: A Practical Approach for Current Sensing

A current sensor circuit intended for integrated smart-power applications featuring galvanic isolation is devised. It is based on magnetic detection using the CMOS compatible split-drain transistors (MAGFET) that provides linear output current versus magnetic field from DC to several MHz range. An integrated sensor built in 0.35 mum CMOS technology presented an output conversion factor of 500 nA/A, corner frequency around 1 MHz and thermal spectral density of 60 pA/radicHz for a power dissipation of less than 15 mW

Bias dependence of noise correlation in MAGFETs

In this paper, measurement results of noise power spectral density in p-channel split-drain MAGFETs operating under various levels of bias current are presented and discussed. It has been observed that correlation increases for decreasing levels of bias current. For currents below 5 /spl mu/A, noise correlation is higher than 50%, rising rapidly towards total correlation. These results indicate that this type of magnetic sensor can be used for low level detection, contradicting what has been so far mentioned in the literature. Measurements were made for bias current ranging from 2 /spl mu/A to circa 70 /spl mu/A using MAGFETs manufactured in 0.8 /spl mu/m CMOS with geometric aspect ratios of 10 /spl mu/m/10 /spl mu/m, 24 /spl mu/m/24 /spl mu/m and 24 /spl mu/m/30 /spl mu/m.

Transversal noise current in split-drain transistors

An excess noise current in CMOS MAGFET split drain transistor is investigated and a new noise model is proposed. It is based on the existence of the transversal noise current that stems from the inversion charge from the MOS transistor channel. This noise current along with the one predicted by the classical MOS transistor produces the total split-drain noise current. This noise current impacts the signal-to-noise ratio and minimum detectable magnetic field, parameters of interest in CMOS-based magnetic sensors. Noise measurement were applied to verify the combined effect of this noise currents. Essentially, it has been observed that a negative correlation between drain currents takes place in split-drain transistor operating in saturation region. Noise voltage power spectral density (Voltage-PSD) measurements were made for split-drain MAGFETs manufactured in 0.8mum, 0.6mum and 0.35mum CMOS with geometric aspect ratio of 10mum/10mum, 24mum/30mum and 10mum/10mum, respectively

Application of the ZVS-PWM commutation cell to a full-bridge DC-DC converter

This paper presents the analysis and design procedures of a new DC-DC full bridge PWM converter using the ZVS-PWM commutation cell to achieve soft switching. Experimental results obtained from a laboratory prototype rated 1500 W are also presented. It is demonstrated that the inclusion of the auxiliary switches do not modify the PWM switching pattern. Bench tests on the prototype confirm that the proposed circuit exhibits high efficiency and behaves as a constant voltage source over an extended power output range.