F Di Paolo

Complete and Systematic Simulation Tools for Frequency Divider Design

In this study, a two-stage simulation method is presented for the efficient design of frequency dividers using harmonic balance. The first stage uses a modified conversion matrix approach to select the subharmonic loads of the active element enabling the frequency division by a given order N. The second stage makes use of an auxiliary generator to obtain and modify the sub-harmonic-power curve versus the input power or input frequency. Systematic simulation tools are used to eliminate common hysteresis phenomena, which require additional constraints to minimize the disturbance of the original frequency-division bands and output power. A harmonic-balance technique to distinguish between subcritical flip bifurcations, associated with hystereses, and supercritical ones is presented, to our knowledge, for the first time. A technique is also derived to transform subcritical bifurcations into supercritical ones. The techniques have been successfully applied to a frequency divider by 2 at 630 MHz.

Large-signal stability of oscillators by the conversion matrix method

In this paper a method for the control of the stability of power amplifiers is extended to oscillators under large-signal conditions. It is based on the conversion matrix of the oscillator, computed from a harmonic balance simulation. This allows the suppression of possible spurious frequencies or the intentional generation of spurious signals (e.g. at sub-harmonic frequency).

A Reflection-Type Biphase Modulator with Balanced Loads

In this contribution a new balanced biphase modulator topology is presented. The new biphase modulator allows the reduction of the resulting chip area occupation by using 3 couplers only, in contrast with traditional reflection-type balanced biphase modulators with 4 couplers, and exhibiting comparable performances. A 45-65 GHz test vehicle adopting the proposed topology has been designed and realised in monolithic form in 70 nm mHEMT technology, resulting in a 1.8 times 1 mm2 die size. The novel topology and the resulting measured performances of the test vehicle are described in the following.

OUTPUT TRACKING FOR CHUA'S CIRCUIT IN PRESENCE OF DISTURBANCES

In this paper we address the problem of output tracking for a Chuas circuit. The reference waveform is generated by another Chuas circuit. This problem is of interest in chaos communications. The tracking problem can be formulated in the well-known frame of output regulation, allowing also the rejection of a modelled disturbance acting on the system.

Multi-octave high efficiency power amplifier in GaAs technology

A 2-18 GHz MMIC power amplifier has been simulated in GaAs technology, based on a non-uniform distributed transmission line topology. The resulting circuit is a non-uniform distributed power amplifier (NDPA), which uses the power pHEMT process available at WIN semiconductor. The NDPA has been optimized for maximum power and efficiency, and it exhibits 1W (CW) output power, 27% medium drain efficiency and 23% medium PAE in the whole operating bandwidth. The resulting small signal gain is 10 dB. Stability analysis has been performed for internal loops also, resulting in an unconditionally stable amplifier. Considering the available results in literature for similar design, the proposed NDPA gives the highest performances in terms of efficiency and output power in the 2-18 GHz operating bandwidth.